78Q2120C09-CGTR/F Maxim Integrated Products, 78Q2120C09-CGTR/F Datasheet - Page 2

• Manufacturer Part Number: 78Q2120C09-CGTR/F
• Description: Telecom ICs 10-100 Fast Ethernet Transceiver Twisted
• Manufacturer: Maxim Integrated Products

Specifications of 78Q2120C09-CGTR/F

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FUNCTIONAL DESCRIPTION
GENERAL
Power Management
The 78Q2120C has three power saving modes:
Chip power-down is activated by setting the PWRDN
bit in MII register MR0.11 or pulling high the PWRDN
pin. When the chip is in the power-down mode, all
on-chip circuitry is shut off, and the device
consumes minimum power.
down state, the 78Q2120C still responds to
management transactions.
Receive power management (RXCC mode) is
activated by setting the RXCC bit in MII register
MR16.0.
equalizer, the clock recovery phase lock loop (PLL),
and all other receive circuitry will be powered down
when no valid MLT-3 signal is present at the UTP
receive line interface. As soon as a valid signal is
detected, all circuits will automatically be powered
up to resume normal operation. During this mode of
operation, RX_CLK will be inactive when there is no
data being received. Note that the RXCC mode is
not supported during 10BASE-T operation.
Transmit high impedance mode is activated by
setting the TXHIM bit in MII register MR16.12. In this
mode of operation, the transmit UTP drivers are in a
high impedance state and TX_CLK is tri-stated. A
weak internal pull-up is enabled on TX_CLK. The
receive circuitry remains fully operational. The
default state of MR16.12 is a logic low for disabling
the transmit high impedance mode. The transmitter
is fully functional when MR16.12 is cleared.
Analog Biasing and Supply Regulation
The 78Q2120C requires no external component to
generate on-chip bias voltages and currents. High
accuracy is maintained through a closed-loop
trimmed biasing network.
On-chip digital logic runs off an internal voltage
regulator.
required to power-up the device.
regulator is not affected by the power-down mode.
Clock Selection
The 78Q2120C will use the on-chip crystal oscillator
as the clock source if the CKIN pin is tied low. In this
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Chip Power-Down
Receive Power Management
Transmit High Impedance Mode
In this mode of operation, the adaptive
Hence only a single Vcc supply is
While in the power-
The on-chip
©
2009 Teridian Semiconductor Corporation
mode of operation, a 25MHz crystal should be
connected between the XTLP and XTLN pins.
Alternatively, an external 25MHz clock signal can be
connected to the CKIN pin. The chip senses activity
on the CKIN pin, and will automatically configure itself
to use the external clock. In this mode of operation, a
crystal is not required and the XTLP and XTLN pins
should be left floating or connected together.
Transmit Clock Generation
The
synthesizer to generate the transmit clock. In
100BASE-TX operation, the synthesizer multiplies the
reference clock by 5 to obtain the internal 125MHz
serial transmit clock.
generates an internal 20MHz transmit clock by
multiplying the 25MHz reference clock by 4/5. The
synthesizer references either the local 25 MHz crystal
oscillator, or the externally applied clock, depending
on the selected mode of operation.
Receive Signal Qualification
The integrated signal qualifier has separate squelch
and unsquelch thresholds. It also includes a built-in
timer to ensure fast and accurate signal detection and
line noise rejection. Upon detection of two or more
valid 10BASE-T or 100BASE-TX pulses on the line
receive port, signal detect is indicated.
detect threshold is then lowered by about 40%. All
adaptive circuits are released from their initial states
and allowed to lock onto the incoming data.
100BASE-TX operation, signal detect is de-asserted
when no signal is presented for a period of about
1.2us. In 10BASE-T operation, signal detect is de-
asserted whenever no Manchester data is received. In
either case, the signal detect threshold will return to the
squelched level whenever the signal detect indication
is de-asserted. Signal detect is also used to control the
operation of the clock/data recovery circuit to assure
fast acquisition.
Receive Clock Recovery
In 100BASE-TX mode, the 125MHz receive clock is
extracted using a digital DLL-based loop. When no
receive signal is present, the CDR is directed to lock
onto the 125MHz transmit serial clock. When signal
detect is asserted, the CDR will use the received MLT-
3 signal as the clock reference. The recovered clock is
used to re-time the data signal and for conversion of
the data to NRZ format.
In 10BASE-T mode, the 10MHz receive clock is
recovered digitally from the Manchester data using a
DLL locked to the reference clock.
Manchester-coded preambles are detected, the
transmitter
uses
In 10BASE-T mode, it
an
10/100BASE-TX
on-chip
Transceiver
78Q2120C
The signal
frequency
Rev 1.3
When
In