78Q2120 Teridian Semiconductor Corp. (TDK Semiconductor), 78Q2120 Datasheet

78Q2120

Manufacturer Part Number

78Q2120

Description

10/100 Ethernet PHYS

Manufacturer

Teridian Semiconductor Corp. (TDK Semiconductor)

Datasheet

1.78Q2120.pdf (30 pages)

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TDK

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78Q2120C-CGT

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78Q2120C09-64CGT/F

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Download datasheet (261Kb)

DESCRIPTION

The 78Q2120-64CGT is a 10BASE-T/100BASE-TX

Fast Ethernet transceiver. It includes integrated MII,

ENDECs, scrambler/descrambler, dual-speed clock

recovery, and full-featured auto-negotiation functions.

The transmitter includes an on-chip pulse-shaper and

a low-power line driver. The receiver has an adaptive

equalizer and a baseline restoration circuit required

for accurate clock and data recovery. The transceiver

interfaces to Category-5 unshielded twisted pair (Cat-

5 UTP) cabling for 100BASE-TX/10BASE-T and

Category-3 unshielded twisted pair for 10BASE-T,

and is connected to the line media via 1:1 isolation

transformers. No external filter is required. Interface

to the MAC is accomplished through an IEEE-802.3

compliant media independent interface (MII). The

product is fabricated in a BiCMOS process for high

performance and low power operation.

M a n ag em e nt

M II S e ria l

& C o ntro l

T ran sm it

R e ce ive

R eg is ters

In te rface

L og ic

M II

10 0 M

1 0M

M a n che ste r D eco de r,

4 B /5B E nco d er,

5B /4 B D e co de r

S erial/P ara lle l,

M a n che ste r E n co de r

P ara lle l/S e ria l

D e scram ble r,

S e ria l/P arallel

S cram b le r,

P ara lle l/S e ria l,

BLOCK DIAGRAM

R efere nce

R e co very

C lo ck

C K IN

C lo ck

M T L3 E n cod er

C o llisio n D etect

C a rrie r S e n se,

N R Z /N R Z I,

G e n era to r

T X C lo ck

FEATURES

•

10BASE-T/100BASE-TX IEEE-802.3 compliant

TX and RX functions requiring a dual 1:1

isolation transformer interface to the line

Integrated MII, 10BASE-T/100BASE-TX ENDEC,

100BASE-TX scrambler/descrambler, and full-

featured auto-negotiation function

Full duplex operation capable

PCS Bypass supports 5-bit symbol interface

Dual speed clock recovery

Automatic polarity correction during auto-

negotiation and 10BASE-T signal reception

Power-saving

including transmitter disable

LED indicators: LINK,TX,RX,COL,100,10,FDX

User programmable Interrupt pin

64-Pin TQFP (JEDEC LQFP) package

Single 3.3 V ± ± ± ± 0.3V Supply

B ase lin e W a n de r C orre cto r,

V cc

M L T3 D e cod e r,

A da ptive E Q ,

N R Z I/N R Z

P u lse S h ap e r

& F ilte r

N eg otia tio n

A u to

G ro u nd

Ethernet Transceiver

and

1 0 0M

78Q2120-64CGT

1 0M

10/100BASE-TX

R e ceive r

power-down

D rivers

U T P

LE D s

LIN K

T X

R X

C O L

1 00 B T

1 0B T

F D X

T X O P

T X O N

R X IP

R X IN

JUNE 2002

modes

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