PSB21384HV1.3 Infineon Technologies, PSB21384HV1.3 Datasheet - Page 117

• Manufacturer Part Number: PSB21384HV1.3
• Description: Telecom ICs AMuLaw/Speech CODEC w/ ST Transceiver
• Manufacturer: Infineon Technologies

Specifications of PSB21384HV1.3

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.3
3.3.1
3.3.1.1
The 64-byte cyclic XFIFO buffer has variable FIFO block sizes (thresholds) of 16 or 32
bytes, selectable by the XFBS bit in the EXMR register.
There are three different interrupt indications in the ISTAH register concerned with the
transmission of data:
– XPR (Transmit Pool Ready) interrupt, indicating that a data block of up to 16 or 32 byte
– XDU (Transmit Data Underrun) interrupt, indicating that the transmission of the
– XMR (Transmit Message Repeat) interrupt, indicating that the transmission of the
Note: For proper operation the XMR bit must not be masked
Three different control commands are used for transmission of data:
– XTF (Transmit Transparent Frame) command, telling the HDLC controller that up to
– XME (Transmit Message End) command, telling the HDLC controller that the last data
– XRES (Transmitter Reset) command, resetting the HDLC transmitter and clearing the
Optionally two additional status conditions can be read by the host:
– XDOV (Transmit Data Overflow), indicating that the data block size has been
Data Sheet
(block size selected via EXMR:XFBS) can be written to the XFIFO.
An XPR interrupt is generated either
• after an XRES (Transmitter Reset) command (which is issued for example for frame
• when a data block from the XFIFO is transmitted and the corresponding FIFO
current frame has been aborted (seven consecutive ’1’s are transmitted) as the XFIFO
holds no further transmit data. This occurs if the host fails to respond to an XPR
interrupt quickly enough.
complete last frame has to be repeated as a collision on the S bus has been detected
and the XFIFO does not hold the first data bytes of the frame (collision after the 16th
or 32nd byte of the frame, respectively).
16 or 32 byte (according to selected block size) have been written to the XFIFO and
should be transmitted. A start flag is generated automatically.
block written to the XFIFO completes the corresponding frame and should be
transmitted. This implies that according to the selected mode a frame end (CRC +
closing flag) is generated and appended to the frame.
transmit FIFO of any data.
exceeded, i.e. more than 16 or 32 byte were entered and data was overwritten.
abort) or
space is released to accept further data from the host.
Data Transmission
Structure and Control of the Transmit FIFO
General Description
107
HDLC Controller
PSB 21381/2
PSB 21383/4
2001-03-12