PSB21384HV1.3 Infineon Technologies, PSB21384HV1.3 Datasheet - Page 210

• Manufacturer Part Number: PSB21384HV1.3
• Description: Telecom ICs AMuLaw/Speech CODEC w/ ST Transceiver
• Manufacturer: Infineon Technologies

Specifications of PSB21384HV1.3

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Sheet
7.2.5
Value after reset: 08
TR_
CMD
Normally the signals in this register are generated by the layer-1 statemachine. If the
internal layer-1 statemachine is disabled (bit L1SW in TR_CONF = ’1’) this register can
be written by the microcontroller.
XINF
000: Transmit INFO 0
001: Reserved
010: Transmit INFO 1
011: Transmit INFO 3
100: Send continuos pulses (Test Mode 2, frequency of the fundamental mode is
101: Send single pulses (Test Mode 1, frequency of the fundamental mode is 2 kHz)
11x: reserved
DPRIO
0: Priority 8 for D-channel handling
1: Priority 10 for D-channel handling
TDDIS
0: The B- and D-channel data is transmitted transparently to the S/T interface if INFO 3
1: Logical ’1’s are transmitted to the S/T interface in the B- and D-channel data if INFO
PD
0: Transceiver in operational mode
1: Transceiver in power down mode. From the analog part only the level detector is
is being transmitted
3 is being transmitted
active. Additionally no clocks are provided and the complete digital part of the
transceiver is inactive if the CFS bit (see chapter 7.2.12) is set to ’1’
96 kHz)
TR_CMD - Transceiver Command Register
7
... Transmit INFO
... D Channel Priority
...Transmit Data Disable
... Power Down
XINF
H
DPRIO TDDIS
200
PD
Detailed Register Description
LP_A
0
0
PSB 21381/2
PSB 21383/4
RD/WR (34
2001-03-12
H
)