LX128C-32FN208C Lattice, LX128C-32FN208C Datasheet - Page 12
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LX128C-32FN208C
Manufacturer Part Number
LX128C-32FN208C
Description
Analog & Digital Crosspoint ICs 128 I/O Switch Matrix, 1.8V, SERDES, 3.2ns, Pb-Free
Manufacturer
Lattice
Datasheet
1.LX256EV-5FN484C.pdf
(75 pages)
Specifications of LX128C-32FN208C
Maximum Dual Supply Voltage
1.95 V
Minimum Dual Supply Voltage
1.65 V
Mounting Style
SMD/SMT
Number Of Arrays
1
Operating Supply Voltage
1.8 V
Supply Type
Triple
Configuration
128 x 128
Package / Case
FPBGA-208
Data Rate
21 Gbps
Input Level
Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
Output Level
Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Product
Digital Crosspoint
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lattice Semiconductor
Table 3. ispGDX2 Supported I/O Standards
The dedicated inputs support a subset of the sysIO standards indicated in Table 4. These inputs are associated
with a bank consistent with their location.
Table 4. I/O Standards Supported by Dedicated Inputs
For more information on the sysIO capability, please refer to Lattice technical note number TN1000, sysIO Design
and Usage Guidelines.
sysCLOCK PLL
The sysCLOCK PLL circuitry consists of Phase-Lock Loops (PLLs) along the various dividers and reset and feed-
back signals associated with the PLLs. This feature gives the user the ability to synthesize clock frequencies and
generate multiple clock signals for routing within the device. Furthermore, it can generate clock signals that are
deskewed either at the board level or the device level. Figure 6 shows the ispGDX2 PLL block diagram.
Each PLL has a set of PLL_RST, PLL_FBK and PLL_LOCK signals. In order to facilitate the multiply and divide
capabilities of the PLL, each PLL has associated dividers. The M divider is used to divide the clock signal, while the
LVCMOS 3.3
LVCMOS 2.5
LVCMOS 1.8
LVTTL
PCI 3.3
PCI -X
AGP-1X
SSTL3 class I & II
SSTL2 class I & II
CTT 3.3
CTT 2.5
HSTL class I
HSTL class III
HSTL class IV
GTL+
LVPECL
LVDS
Bus-LVDS
1. LVPECL drivers require three resistor pack (see Figure 17).
2. Depending on the driving LVPECL output specification, GDX2 LVPECL input driver may require terminating resistors.
3. For additional information on LVPECL refer to Lattice technical note number TN1000, sysIO Design and Usage Guidelines.
Global OE Pins
Global MUX Select Pins
Resetb
Global Clock/Clock Enables
ispJTAG™ Port
TOE
1. LVCMOS as defined by the V
2. No PCI clamp.
sysIO Standard
1, 2, 3
CCJ
pin voltage.
Nominal V
1.8/2.5/3.3V
LVCMOS
2.5/3.3V
2.5/3.3V
3.3V
2.5V
1.8V
3.3V
3.3V
3.3V
3.3V
3.3V
2.5V
3.3V
2.5V
1.5V
1.5V
1.5V
3.3V
Yes
Yes
Yes
Yes
Yes
Yes
1
CCO
9
Nominal V
1.25V
1.25V
0.75V
LVDS
1.5V
1.5V
0.9V
0.9V
1.0V
Yes
No
No
No
No
No
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REF
ispGDX2 Family Data Sheet
All other ASIC I/Os
Nominal V
1.25V
1.25V
0.75V
0.75V
1.5V
1.5V
1.5V
1.5V
Yes
Yes
Yes
Yes
No
No
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—
—
—
—
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2
2
2
2
TT