LAN91C100FDTQFP SMSC, LAN91C100FDTQFP Datasheet - Page 28

• Manufacturer Part Number: LAN91C100FDTQFP
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C100FDTQFP

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 7 V
• Supply Voltage (min): 0.3 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BANK 1
BANK 1
Revision 1.0 (09-22-08)
4 THROUGH 9
OFFSET
BYTE
BYTE
HIGH
LOW
OFFSET
FULL STEP - This bit is a general purpose output port. Its inverse value drives pin nFSTEP and it is
typically connected to SEL pin of the LAN83C694. It can be used to select the signaling mode for the AUI
or as a general purpose non-volatile configuration pin. Defaults low.
AUI SELECT - This bit is a general purpose output port. Its value drives pin AUISEL and it is typically
connected to MODE1 pin of the LAN83C694. It can be used to select AUI vs. 10BASE-T, or as a general
purpose non-volatile configuration pin. Defaults low.
Reserved - Must be 0.
INT SEL1-0 - Used to select one out of four interrupt pins. The three unused interrupts are tristated.
This register holds the I/O address decode option chosen for the LAN91C100FD. It is part of the EEPROM
saved setup and is not usually modified during run-time.
A15 - A13 and A9 - A5 - These bits are compared against the I/O address on the bus to determine the
IOBASE for the LAN91C100FD‘s registers. The 64k I/O space is fully decoded by the LAN91C100FD
down to a 16 location space, therefore the unspecified address lines A4, A10, A11 and A12 must be all
zeros.
All bits in this register are loaded from the serial EEPROM.
(namely, the high byte defaults to 18h).
Reserved - Must be 0.
These registers are loaded starting at word location 20h of the EEPROM upon hardware reset or
EEPROM reload. The registers can be modified by the software driver, but a STORE operation will not
modify the EEPROM Individual Address contents. Bit 0 of Individual Address 0 register corresponds to the
first bit of the address on the cable.
2
A15
0
0
BASE ADDRESS REGISTER
INDIVIDUAL ADDRESS
INT SEL1
A14
0
0
0
0
1
1
REGISTERS
NAME
NAME
A13
0
0
DATASHEET
INT SEL0
Reserved
Page 28
A9
0
1
0
1
1
0
A8
READ/WRITE
READ/WRITE
1
0
FEAST Fast Ethernet Controller with Full Duplex Capability
INTERRUPT PIN
TYPE
TYPE
The I/O base decode defaults to 300h
INTR0
INTR1
INTR2
INTR3
USED
A7
0
0
A6
0
0
SMSC LAN91C100FD Rev. D
SYMBOL
SYMBOL
BAR
IAR
A5
0
1
1