LAN91C100FDTQFP SMSC, LAN91C100FDTQFP Datasheet - Page 3

• Manufacturer Part Number: LAN91C100FDTQFP
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C100FDTQFP

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 7 V
• Supply Voltage (min): 0.3 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table Of Contents
Chapter 1
Chapter 2
Chapter 3
Chapter 4
4.1
4.2
Chapter 5
5.1
5.2
5.3
5.4
5.5
5.6
Chapter 6
Chapter 7
7.1
7.2
7.3
7.4
Chapter 8
8.1
8.2
Chapter 9
Chapter 10
List of Figures
Figure 3.1 - LAN91C100FD Block Diagram .................................................................................................................13
Figure 3.2 - LAN91C100FD System Diagram ..............................................................................................................14
Figure 4.1 - LAN91C100FD Internal Bock diagram with Data Path..............................................................................18
Figure 5.1 - Data Packet Format ..................................................................................................................................19
Figure 5.2 - Interrupt Structure .....................................................................................................................................37
Figure 5.3 - Interrupt Service Routine ..........................................................................................................................44
Figure 5.4 - RX INTR ...................................................................................................................................................45
Figure 5.5 - TX INTR....................................................................................................................................................46
Figure 5.6 - TXEMPTY INTR (Assumes Auto release Option Selected) ......................................................................47
Figure 5.7 - Drive Send and Allocate Routines ............................................................................................................48
Figure 5.8 - Interrupt Generation for Transmit, Receive, MMU ....................................................................................51
Figure 6.1 - 64 X 16 Serial EEPROM Map...................................................................................................................54
SMSC LAN91C100FD Rev. D
FEAST Fast Ethernet Controller with Full Duplex Capability
4.1.1
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
Description of Block........................................................................................................................... 15
CSMA/CD BLOCK............................................................................................................................. 15
Packet Format in Buffer Memory ...................................................................................................... 19
Typical Flow of Events for Transmit (Auto Release = 0)................................................................... 41
Typical Flow of Events for Transmit (Auto Release = 1)................................................................... 42
Typical Flow of Events for Receive ................................................................................................... 43
Memory Partitioning .......................................................................................................................... 48
Interrupt Generation .......................................................................................................................... 49
Fast Ethernet Slave Adapter ............................................................................................................. 55
VL Local Bus 32 Bit Systems ............................................................................................................ 55
High End ISA or Non-Burst EISA Machines...................................................................................... 58
EISA 32 Bit SLAVEEISA 32 Bit Slave............................................................................................... 60
Maximum Guaranteed Ratings* ........................................................................................................ 63
DC Electrical Characteristics............................................................................................................. 63
Clock Generator Block............................................................................................................................15
DMA Block..............................................................................................................................................15
Arbiter Block ...........................................................................................................................................15
MMU Block .............................................................................................................................................16
BIU Block................................................................................................................................................16
MAC-PHY Interface Block ......................................................................................................................16
MII Management Interface Block ............................................................................................................17
Serial EEPROM Interface .......................................................................................................................17
General Description ............................................................................................................. 5
Pin Configuration................................................................................................................. 6
Description of Pin Functions ............................................................................................... 7
Functional Description....................................................................................................... 15
Data Structures and Registers .......................................................................................... 19
Board Setup Information .................................................................................................. 52
Application Considerations ............................................................................................... 55
Operational Description .................................................................................................... 63
Timing Diagrams................................................................................................................ 66
Package Outlines............................................................................................................. 76
DATASHEET
Page 3
Revision 1.0 (09-22-08)