PSMN030-150B,118 NXP Semiconductors, PSMN030-150B,118 Datasheet - Page 2

MOSFET N-CH 150V 55.5A SOT404

PSMN030-150B,118

Manufacturer Part Number
PSMN030-150B,118
Description
MOSFET N-CH 150V 55.5A SOT404
Manufacturer
NXP Semiconductors
Series
TrenchMOS™r
Datasheet

Specifications of PSMN030-150B,118

Package / Case
D²Pak, TO-263 (2 leads + tab)
Mounting Type
Surface Mount
Power - Max
250W
Fet Type
MOSFET N-Channel, Metal Oxide
Gate Charge (qg) @ Vgs
98nC @ 10V
Vgs(th) (max) @ Id
4V @ 1mA
Current - Continuous Drain (id) @ 25° C
55.5A
Drain To Source Voltage (vdss)
150V
Fet Feature
Standard
Rds On (max) @ Id, Vgs
30 mOhm @ 25A, 10V
Minimum Operating Temperature
- 55 C
Configuration
Single
Transistor Polarity
N-Channel
Resistance Drain-source Rds (on)
0.03 Ohm @ 10 V
Drain-source Breakdown Voltage
150 V
Gate-source Breakdown Voltage
+/- 20 V
Continuous Drain Current
55.5 A
Power Dissipation
250000 mW
Maximum Operating Temperature
+ 175 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
934056598118::PSMN030-150B /T3::PSMN030-150B /T3
NXP Semiconductors
2. Pinning information
Table 2.
[1]
3. Ordering information
Table 3.
4. Limiting values
Table 4.
In accordance with the Absolute Maximum Rating System (IEC 60134).
PSMN030-150B
Product data sheet
Pin
1
2
3
mb
Type number
PSMN030-150B
Symbol
V
V
V
I
I
P
T
T
Source-drain diode
I
I
Avalanche ruggedness
E
I
D
DM
S
SM
AS
stg
j
DS
DGR
GS
tot
DS(AL)S
It not possible to make a connection to pin 2.
Symbol Description
G
D
S
D
Pinning information
Ordering information
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive drain-source
avalanche energy
non-repetitive avalanche current
gate
drain
source
mounting base; connected to drain
D2PAK
Package
Name
[1]
Description
plastic single-ended surface-mounted package (D2PAK); 3 leads
(one lead cropped)
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 13 December 2010
Conditions
T
T
T
T
pulsed; T
T
T
pulsed; T
V
V
t
V
R
p
j
j
mb
mb
mb
mb
GS
sup
sup
GS
Simplified outline
= 100 µs
≥ 25 °C; T
≤ 175 °C; T
N-channel TrenchMOS SiliconMAX standard level FET
= 25 °C
= 100 °C
= 25 °C
= 25 °C
= 10 V; T
= 50 Ω; unclamped
≤ 50 V; unclamped; R
≤ 50 V; V
SOT404 (D2PAK)
mb
mb
= 25 °C
= 25 °C
j
≤ 175 °C
j
j(init)
GS
≥ 25 °C; R
1
= 10 V; T
mb
2
= 25 °C; I
3
GS
j(init)
GS
D
= 20 kΩ
= 35 A;
= 50 Ω;
= 25 °C;
PSMN030-150B
Graphic symbol
Min
-
-
-20
-
-
-
-
-55
-55
-
-
-
-
mbb076
G
© NXP B.V. 2010. All rights reserved.
175
175
Version
SOT404
Max
150
150
20
55.5
39
222
250
55.5
222
300
35
D
S
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
A
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