NTD60N02R-35G ON Semiconductor, NTD60N02R-35G Datasheet

MOSFET N-CH 25V 8.5A IPAK

NTD60N02R-35G

Manufacturer Part Number
NTD60N02R-35G
Description
MOSFET N-CH 25V 8.5A IPAK
Manufacturer
ON Semiconductor
Datasheet

Specifications of NTD60N02R-35G

Fet Type
MOSFET N-Channel, Metal Oxide
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
10.5 mOhm @ 20A, 10V
Drain To Source Voltage (vdss)
25V
Current - Continuous Drain (id) @ 25° C
8.5A
Vgs(th) (max) @ Id
2V @ 250µA
Gate Charge (qg) @ Vgs
14nC @ 4.5V
Input Capacitance (ciss) @ Vds
1330pF @ 20V
Power - Max
1.25W
Mounting Type
Through Hole
Package / Case
IPak, TO-251, DPak (3 straight short leads + tab)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
NTD60N02R
Power MOSFET
62 A, 25 V, N−Channel, DPAK
Features
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using 0.5 in sq drain pad size.
2. When surface mounted to an FR4 board using the minimum recommended
MAXIMUM RATINGS
© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 12
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Thermal Resistance
Total Power Dissipation @ T
Drain Current
Thermal Resistance
Total Power Dissipation @ T
Drain Current − Continuous @ T
Thermal Resistance
Total Power Dissipation @ T
Drain Current − Continuous @ T
Operating and Storage Temperature
Single Pulse Drain−to−Source Avalanche Energy
− Starting T
(V
I
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
L
High−Efficiency DC−DC Converters
Planar HD3e Process for Fast Switching Performance
Low R
Low C
Low Gate Charge
Optimized for High Side Switching Requirements in
Pb−Free Packages are Available
pad size.
DD
= 11 Apk, L = 1.0 mH, R
Junction−to−Case
Continuous @ T
Continuous @ T
Continuous @ T
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
= 50 Vdc, V
DS(on)
iss
J
to Minimize Driver Loss
= 25°C
to Minimize Conduction Loss
GS
C
C
A
= 10.0 Vdc,
Rating
= 25°C, Limited by Wires
= 25°C, Chip
= 25°C, Limited by Package
(T
J
G
= 25°C unless otherwise noted)
A
A
= 25 W)
C
= 25°C
= 25°C
= 25°C
A
A
= 25°C
= 25°C
Symbol
T
V
R
R
R
J
V
E
T
P
P
P
, and
DSS
T
I
I
I
I
I
qJC
qJA
qJA
stg
GS
AS
D
D
D
D
D
D
D
D
L
−55 to
Value
1.87
10.5
1.25
±20
120
175
260
2.6
8.5
25
58
62
50
32
80
60
1
°C/W
°C/W
Unit
C/W
Vdc
Vdc
mJ
°C
°C
W
W
W
A
A
A
A
A
(Surface Mount)
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
1 2
CASE 369AA
V
Gate
STYLE 2
(BR)DSS
25 V
3
DPAK
1
Drain
Drain
ORDERING INFORMATION
Y
WW
T60N02R = Device Code
G
4
2
4
G
& PIN ASSIGNMENTS
MARKING DIAGRAM
http://onsemi.com
3
Source
8.4 mW @ 10 V
(Straight Lead)
R
CASE 369AC
N−Channel
DS(on)
= Year
= Work Week
= Pb−Free Package
1
3 IPAK
D
Publication Order Number:
2 3
TYP
4
S
Gate
1
Drain
Drain
NTD60N02R/D
(Straight Lead)
4
2
CASE 369D
STYLE 2
I
1
D
DPAK
62 A
3
Source
2
MAX
3
4

Related parts for NTD60N02R-35G

NTD60N02R-35G Summary of contents

Page 1

... R TYP I MAX DS(on 8 N−Channel CASE 369AC CASE 369D 3 IPAK DPAK (Straight Lead) (Straight Lead) STYLE 2 MARKING DIAGRAM & PIN ASSIGNMENTS 4 Drain Source Gate Drain Source = Year = Work Week = Pb−Free Package Publication Order Number: NTD60N02R/D ...

Page 2

... Gate Charge SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage ( Adc Reverse Recovery Time Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures. NTD60N02R (T = 25°C unless otherwise noted) J Symbol Vdc Adc) (Note 3) D ...

Page 3

... Figure 3. On−Resistance versus Gate−to−Source Voltage 2 1.8 GS 1.6 1.4 1.2 1.0 0.8 0.6 −50 − JUNCTION TEMPERATURE (°C) J Figure 5. On−Resistance Variation with Temperature NTD60N02R TYPICAL CHARACTERISTICS 120 25° 5.0 V 100 4 175° 2 Figure 2. Transfer Characteristics 0. 25° ...

Page 4

... R , GATE RESISTANCE (W) G Figure 9. Resistive Switching Time Variation versus Gate Resistance 100 V GS SINGLE PULSE 0.1 Figure 11. Maximum Rated Forward Biased Safe Operating Area NTD60N02R 25° iss oss 1 C rss Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge ...

Page 5

... ORDERING INFORMATION Order Number NTD60N02R NTD60N02RG NTD60N02RT4 NTD60N02RT4G NTD60N02R−1 NTD60N02R−1G NTD60N02R−35 NTD60N02R−35G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NTD60N02R P (pk ...

Page 6

... 0.13 (0.005) M 5.80 0.228 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. NTD60N02R PACKAGE DIMENSIONS DPAK CASE 369AA−01 ISSUE A SEATING −T− PLANE SOLDERING FOOTPRINT* 6.20 3.0 0.244 ...

Page 7

... SEATING PLANE NTD60N02R PACKAGE DIMENSIONS 3 IPAK, STRAIGHT LEAD CASE 369AC−01 ISSUE 0.13 (0.005) W http://onsemi.com 7 NOTES: 1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.. CONTROLLING DIMENSION: INCH. 3. SEATING PLANE IS ON TOP OF DAMBAR POSITION. 4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE. ...

Page 8

... S 0.025 0.040 0.63 1.01 V 0.035 0.050 0.89 1.27 Z 0.155 −−− 3.93 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NTD60N02R/D ...

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