NTY100N10G ON Semiconductor, NTY100N10G Datasheet - Page 4

• Manufacturer Part Number: NTY100N10G
• Description: MOSFET N-CH 100V 123A TO-264
• Manufacturer: ON Semiconductor

Specifications of NTY100N10G

• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Standard
• Rds On (max) @ Id, Vgs: 10 mOhm @ 50A, 10V
• Drain To Source Voltage (vdss): 100V
• Current - Continuous Drain (id) @ 25° C: 123A
• Vgs(th) (max) @ Id: 4V @ 250µA
• Gate Charge (qg) @ Vgs: 350nC @ 10V
• Input Capacitance (ciss) @ Vds: 10110pF @ 25V
• Power - Max: 313W
• Mounting Type: Through Hole
• Package / Case: TO-264-3, TO-3BPL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate
of average input current (I
rudimentary analysis of the drive circuit so that
t = Q/I
During the rise and fall time interval when switching a
resistive load, V
known as the plateau voltage, V
times may be approximated by the following:
t
t
where
V
V
R
and Q
During the turn−on and turn−off delay times, gate current
is not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation
for voltage change in an RC network. The equations are:
t
t
r
f
d(on)
d(off)
GG
GG
G
= Q
= Q
Switching behavior is most easily modeled and predicted
= the gate drive resistance
= the gate drive voltage, which varies from zero to
= R
2
2
= R
2
G(AV)
x R
x R
and V
G
G
G
G
C
C
/(V
/V
iss
iss
GSP
GSP
GG
In [V
In (V
GS
are read from the gate charge curve.
− V
remains virtually constant at a level
GG
GG
GSP
/(V
/V
)
GSP
GG
G(AV)
)
− V
SGP
) can be made from a
. Therefore, rise and fall
GSP
)]
POWER MOSFET SWITCHING
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4
The capacitance (C
at a voltage corresponding to the off−state condition when
calculating t
the on−state when calculating t
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but
since di/dt is a function of drain current, the mathematical
solution is complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves
would maintain a value of unity regardless of the switching
speed. The circuit used to obtain the data is constructed to
minimize common inductance in the drain and gate circuit
loops and is believed readily achievable with board
mounted components. Most power electronic loads are
inductive; the data in the figure is taken with a resistive
load, which approximates an optimally snubbed inductive
load. Power MOSFETs may be safely operated into an
inductive load; however, snubbing reduces switching
losses.
At high switching speeds, parasitic circuit elements
The resistive switching time variation versus gate
d(on)
and is read at a voltage corresponding to
iss
) is read from the capacitance curve
d(off)
.