SI3201-FSR Silicon Laboratories Inc, SI3201-FSR Datasheet - Page 107

• Manufacturer Part Number: SI3201-FSR
• Description: SLIC 1-CH 60dB 41mA 3.3V/5V 16-Pin SOIC EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3201-FSR

• Package: 16SOIC EP
• Number Of Channels Per Chip: 1
• Longitudinal Balanced: 60 dB
• Loop Current: 41 mA
• Minimum Operating Supply Voltage: 3.13 V
• Typical Operating Supply Voltage: 3.3|5 V
• Typical Supply Current: 88 mA

4.3. SLIC Control
See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values
are represented in 2s-complement format.
Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read
Addr.
Addr. D15
15
16
17
18
15
16
17
18
19
20
21
22
23
24
25
26
27
64
66
and written but should be written to zeroes.
Loop Closure Threshold.
Loop closure detection threshold. This register defines the upper bounds threshold if hys-
teresis is enabled (direct Register 108, bit 0). The range is 0–80 mA in 1.27 mA steps.
Ring Trip Threshold.
Ring trip detection threshold during ringing.
Common Mode Minimum Threshold for Speed-Up.
This register defines the negative common mode voltage threshold. Exceeding this
threshold enables a wider bandwidth of dc linefeed control for faster settling times. The
range is 0–23.625 V in 0.375 V steps.
Common Mode Maximum Threshold for Speed-Up.
This register defines the positive common mode voltage threshold. Exceeding this
threshold enables a wider bandwidth of dc linefeed control for faster settling times. The
range is 0–23.625 V in 0.375 V steps.
D14
D13
Table 41. SLIC Control Indirect Registers Description
Table 40. SLIC Control Indirect Registers Summary
LCRTL[5:0]
D12
RPTP[5:0]
LCRT[5:0]
VMIND[3:0]
PPT12[7:0]
PPT34[7:0]
PPT56[7:0]
VCMR[3:0]
D11
D10
CMH[5:0]
CML[5:0]
NCLR[12:0]
NRTP[12:0]
NQ12[12:0]
NQ34[12:0]
NQ56[12:0]
Description
D9
Rev. 1.0
D8
D7
D6
D5
D4
D3
D2
Reference Page
Si3216
D1
32
42
D0
107