8543BGILF Integrated Device Technology (Idt), 8543BGILF Datasheet - Page 13

• Manufacturer Part Number: 8543BGILF
• Description: Clock Driver 2-IN LVDS 20-Pin TSSOP Tube
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 8543BGILF

• Package: 20TSSOP
• Configuration: 1 x 2:1
• Input Signal Type: CML/HCSL/LVDS/LVHSTL/LVPECL/SSTL
• Maximum Output Frequency: 650 MHz
• Operating Supply Voltage: 3.3 V

Recommendations for Unused Input and Output Pins
Inputs:
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to
ground.
PCLK/nPCLK Inputs
For applications not requiring the use of the differential input, both
PCLK and nPCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from PCLK to
ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 5. In a 100Ω
differential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver input.
Figure 5. Typical LVDS Driver Termination
IDT™ / ICS™ LVDS FANOUT BUFFER
ICS8543I
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
3.3V
LVDS Driver
100Ω Differential Transmission Line
50Ω
50Ω
R1
100Ω
13
Outputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, there should
be no trace attached.
For a multiple LVDS outputs buffer, if only partial outputs are used,
it is recommended to terminate the unused outputs.
+
–
3.3V
ICS8543BGI REV. E SEPTEMBER 9, 2008