8543BGILF Integrated Device Technology (Idt), 8543BGILF Datasheet - Page 3

• Manufacturer Part Number: 8543BGILF
• Description: Clock Driver 2-IN LVDS 20-Pin TSSOP Tube
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 8543BGILF

• Package: 20TSSOP
• Configuration: 1 x 2:1
• Input Signal Type: CML/HCSL/LVDS/LVHSTL/LVPECL/SSTL
• Maximum Output Frequency: 650 MHz
• Operating Supply Voltage: 3.3 V

Function Tables
Table 3A. Control Input Function Table
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK/nCLK and PCLK/nPCLK inputs as described in Table 3B.
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels.
IDT™ / ICS™ LVDS FANOUT BUFFER
nCLK, nPCLK
ICS8543I
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
CLK, PCLK
Biased; NOTE 1
Biased; NOTE 1
nQ0:nQ3
CLK or PCLK
CLK_EN
Q0:Q3
OE
0
1
1
1
1
0
1
0
1
Inputs
nCLK or nPCLK
Biased; NOTE 1
Biased; NOTE 1
CLK_EN
X
0
0
1
1
1
0
0
1
Inputs
Disabled
CLK_SEL
Q[0:3]
HIGH
HIGH
HIGH
LOW
LOW
LOW
X
0
1
0
1
Outputs
3
nQ[0:3]
HIGH
HIGH
HIGH
LOW
LOW
LOW
Selected Source
PCLK/nPCLK
PCLK/nPCLK
CLK/nCLK
CLK/nCLK
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Differential to Differential
Differential to Differential
Input to Output Mode
Disabled; Low
Disabled; Low
Enabled
Enabled
ICS8543BGI REV. E SEPTEMBER 9, 2008
Q0:Q3
Hi-Z
Enabled
Outputs
Disabled; High
Disabled; High
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
nQ0:nQ3
Enabled
Enabled
Inverting
Inverting
Polarity
Hi-Z