SI5326B-C-GM Silicon Laboratories Inc, SI5326B-C-GM Datasheet - Page 24

• Manufacturer Part Number: SI5326B-C-GM
• Description: ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR, 2 OUT
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5326B-C-GM

• Pll: Yes
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 808MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 1.71 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-QFN
• Frequency-max: 808MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1745

Si5326
Reset value = 0000 0101
24
Register 3.
Name
Type
7:6
3:0
Bit
Bit
5
4
CKSEL_REG
SQ_ICAL
Reserved
DHOLD
CKSEL_REG [1:0]
Name
D7
[1:0]
R/W
CKSEL_REG.
If the device is operating in register-based manual clock selection mode
(AUTOSEL_REG = 00), and CKSEL_PIN = 0, then these bits select which input clock
will be the active input clock. If CKSEL_PIN = 1 and AUTOSEL_REG = 00, the CS_CA
input pin continues to control clock selection and
00: CKIN_1 selected.
01: CKIN_2 selected.
10: Reserved
11: Reserved
DHOLD.
Forces the part into digital hold. This bit overrides all other manual and automatic clock
selection controls.
0: Normal operation.
1: Force digital hold mode. Overrides all other settings and ignores the quality of all of the
input clocks.
SQ_ICAL.
This bit determines if the output clocks will remain enabled or be squelched (disabled)
during an internal calibration. See Table 8 on page 19.
0: Output clocks enabled during ICAL.
1: Output clocks disabled during ICAL.
Reserved.
D6
DHOLD
R/W
D5
SQ_ICAL
R/W
Rev. 1.0
D4
Function
D3
CKSEL_REG is of no consequence
D2
Reserved
R
D1
.
D0