SI5326B-C-GM Silicon Laboratories Inc, SI5326B-C-GM Datasheet - Page 30
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SI5326B-C-GM
Manufacturer Part Number
SI5326B-C-GM
Description
ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR, 2 OUT
Manufacturer
Silicon Laboratories Inc
Type
Clock Multiplierr
Datasheet
1.SI5326B-C-GM.pdf
(72 pages)
Specifications of SI5326B-C-GM
Pll
Yes
Input
Clock
Output
CML, CMOS, LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
2:2
Differential - Input:output
Yes/Yes
Frequency - Max
808MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
1.71 V ~ 3.63 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
36-QFN
Frequency-max
808MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
336-1745
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI5326B-C-GM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Part Number:
SI5326B-C-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Si5326
Reset value = 0100 0000
Reset value = 0000 0000
30
Register 11.
Register 16.
Name
Name
Type
Type
7:2
7:0
Bit
Bit
Bit
Bit
1
0
CLAT [7:0]
Reserved
PD_CK2
PD_CK1
Name
Name
D7
D7
Reserved.
PD_CK2.
This bit controls the powerdown of the CKIN2 input buffer.
0: CKIN2 enabled
1: CKIN2 disabled
PD_CK1.
This bit controls the powerdown of the CKIN1 input buffer.
0: CKIN1 enabled
1: CKIN1 disabled
CLAT [7:0].
With INCDEC_PIN = 0, this register sets the phase delay for CKOUTn in units of
1/Fosc. This can take as long as 20 seconds.
01111111 = 127/Fosc (2s compliment)
00000000 = 0
10000000 = -128/Fosc (2s compliment)
If NI_HS[2:0] = 000, increasing CLAT does not work.
D6
D6
D5
D5
Reserved
R
Rev. 1.0
D4
D4
CLAT [7:0]
R/W
Function
Function
D3
D3
D2
D2
PD_CK2
R/W
D1
D1
PD_CK1
R/W
D0
D0