MT46V16M16P-5B:K TR Micron Technology Inc, MT46V16M16P-5B:K TR Datasheet - Page 59

• Manufacturer Part Number: MT46V16M16P-5B:K TR
• Description: DRAM Chip DDR SDRAM 256M-Bit 16Mx16 2.6V 66-Pin TSOP T/R
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V16M16P-5B:K TR

• Package: 66TSOP
• Density: 256 Mb
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 2.6 V
• Maximum Clock Rate: 400 MHz
• Maximum Random Access Time: 0.7 ns
• Operating Temperature: 0 to 70 °C

CAS Latency (CL)
Figure 24:
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
CAS Latency
Note:
The CL is the delay, in clock cycles, between the registration of a READ command and
the availability of the first bit of output data. The latency can be set to 2, 2.5, or 3 (-5B
only) clocks, as shown in Figure 24. Reserved states should not be used, as unknown
operation or incompatibility with future versions may result.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available nominally coincident with clock edge n + m. Table 35 on page 58 indi-
cates the operating frequencies at which each CL setting can be used.
Command
Command
Command
BL = 4 in the cases shown; shown with nominal
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
CK
CK
CK
READ
READ
READ
T0
T0
T0
CL = 2
CL = 3
CL = 2.5
NOP
NOP
NOP
T1
T1
T1
57
Transitioning Data
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
NOP
NOP
T2
T2
T2
256Mb: x4, x8, x16 DDR SDRAM
T2n
T2n
t
AC,
t
DQSCK, and
NOP
NOP
NOP
T3
T3
T3
Don’t Care
T3n
T3n
T3n
©2003 Micron Technology, Inc. All rights reserved.
t
DQSQ.
Operations