MT47H32M16HR-3 IT:F TR Micron Technology Inc, MT47H32M16HR-3 IT:F TR Datasheet - Page 61

• Manufacturer Part Number: MT47H32M16HR-3 IT:F TR
• Description: DRAM Chip DDR2 SDRAM 512M-Bit 32Mx16 1.8V 84-Pin FBGA T/R
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H32M16HR-3 IT:F TR

• Density: 512 Mb
• Maximum Clock Rate: 667 MHz
• Package: 84FBGA
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 1.8 V
• Maximum Random Access Time: 0.45 ns
• Operating Temperature: -40 to 85 °C
• Organization: 32Mx16
• Address Bus: 15b
• Access Time (max): 450ps
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 250mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Table 31: DDR2-400/533
All units are shown in picoseconds
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. R 12/10 EN
(V/ns)
Slew
Rate
DQ
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
t
125
83
4.0 V/ns
DS
Δ
0
–
–
–
–
–
–
t
DH
45
21
Δ
0
–
–
–
–
–
–
t
125
–11
Notes:
DS
83
3.0 V/ns
Δ
0
–
–
–
–
–
t
–14
DH
45
21
Δ
0
–
–
–
–
–
t
DS,
1. For all input signals, the total
2.
3.
4. Although the total setup time might be negative for slow slew rates (a valid input signal
5. For slew rates between the values listed in this table, the derating values may be ob-
6. These values are typically not subject to production test. They are verified by design and
7. Single-ended DQS requires special derating. The values in Table 33 (page 63) are the
t
sheet value to the derating value listed in Table 31.
t
crossing of V
signal is defined as the slew rate between the last crossing of V
ing of V
between the shaded “V
value (see Figure 26 (page 65)). If the actual signal is later than the nominal slew rate
line anywhere between the shaded “V
line to the actual signal from the AC level to DC level is used for the derating value (see
Figure 27 (page 65)).
t
crossing of V
signal is defined as the slew rate between the last crossing of V
ing of V
between the shaded “DC level to V
rating value (see Figure 28 (page 66)). If the actual signal is earlier than the nominal
slew rate line anywhere between shaded “DC to V
gent line to the actual signal from the DC level to V
value (see Figure 29 (page 66)).
will not have reached V
put signal is still required to complete the transition and reach V
tained by linear interpolation.
characterization.
DQS single-ended slew rate derating with DQS referenced at V
the logic levels
to the AC/DC trip points to DQ referenced to V
Table 36 (page 64). Table 35 provides the V
(
the DQ (
125
–11
–25
t
83
DS nominal slew rate for a rising signal is defined as the slew rate between the last
DH nominal slew rate for a rising signal is defined as the slew rate between the last
t
2.0 V/ns
DS
Δ
0
–
–
–
–
DS
DH Derating Values with Differential Strobe
a
and
t
–14
–31
DH
45
21
Δ
0
–
–
–
–
IL(AC)max
REF(DC)
t
DS
t
DH
a
DQS, DQS# Differential Slew Rate
t
REF(DC)
IL(DC)max
–13
–31
and
DS
95
12
1.8 V/ns
a
Δ
. If the actual signal is always later than the nominal slew rate line
–
1
–
–
–
) for DDR2-533. Table 36 provides the V
t
. If the actual signal is always earlier than the nominal slew rate line
DS
t
DH
b
t
–19
–42
and the first crossing of V
DH
33
12
–2
Δ
and
–
–
–
–
and the first crossing of V
a
) for DDR2-400.
IH[AC]
REF(DC)
t
DH
t
–19
–43
61
DS
24
13
–1
1.6 V/ns
Δ
–
–
–
–
b
/V
. Converting the derated base values from DQ referenced
t
to AC region,” use the nominal slew rate for the derating
DS and
IL[AC]
t
–30
–59
DH
24
10
–7
Δ
–
–
–
–
REF(DC)
at the time of the rising clock transition), a valid in-
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
t
REF(DC)
–31
–74
DH required is calculated by adding the data
DS
25
11
–7
1.4 V/ns
Δ
–
–
–
–
512Mb: x4, x8, x16 DDR2 SDRAM
region,” use the nominal slew rate for the de-
REF
t
IH(AC)min
to AC region,” the slew rate of a tangent
–18
–47
–89
DH
22
-based fully derated values for the DQ
Δ
–
–
–
5
–
REF(DC)
REF
is listed in Table 35 (page 64) and
REF(DC)
–127 –140 –115 –128 –103 –116
Input Slew Rate Derating
t
–19
–62
REF(DC)
23
DS
1.2 V/ns
Δ
.
.
–
–
–
–
5
t
t
REF
DH nominal slew rate for a falling
DS nominal slew rate for a falling
-based fully derated values for
region,” the slew rate of a tan-
t
–35
–77
level is used for the derating
DH
17
–6
Δ
–
–
–
–
© 2004 Micron Technology, Inc. All rights reserved.
IH(DC)min
REF
REF(DC)
t
–50
IH(AC)
DS
17
–7
1.0 V/ns
Δ
–
–
–
–
–
and DQ referenced at
/V
and the first cross-
and the first cross-
t
–23
–65
DH
IL(AC)
Δ
–
–
–
–
–
6
.
t
–38
DS
0.8 V/ns
Δ
5
–
–
–
–
–
–
t
–11
–53
DH
Δ
–
–
–
–
–
–