MT48LC4M16A2P-75:G Micron Technology Inc, MT48LC4M16A2P-75:G Datasheet - Page 34

• Manufacturer Part Number: MT48LC4M16A2P-75:G
• Description: DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr
• Series: -r

Specifications of MT48LC4M16A2P-75:G

• Density: 64 Mb
• Maximum Clock Rate: 133 MHz
• Package: 54TSOP-II
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: 0 to 70 °C
• Organization: 4Mx16
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 140mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-TSOP (0.400", 10.16mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Power-Down
Figure 24:
Figure 25:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
Terminating a WRITE Burst
PRECHARGE Command
Note:
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND
INHIBIT when no accesses are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when
there is a row active in any bank, this mode is referred to as active power-down. Entering
power-down deactivates the input and output buffers, excluding CKE, for maximum
power savings while in standby. The device may not remain in the power-down state
longer than the refresh period (
performed in this mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting
COMMAND
A0–A9
BA0,1
RAS#
CAS#
ADDRESS
WE#
CKE
CLK
A10
CS#
DQMs are LOW.
CLK
TRANSITIONING DATA
DQ
HIGH
VALID ADDRESS
BANK,
WRITE
COL n
D
T0
n
IN
TERMINATE
Bank Selected
BURST
T1
All Banks
ADDRESS
BANK
DON’T CARE
COMMAND
(ADDRESS)
(DATA)
NEXT
T2
34
DON’T CARE
t
REF or
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
REF
t
CKS). See Figure 26 on page 35.
AT
) since no refresh operations are
64Mb: x4, x8, x16 SDRAM
©2000 Micron Technology, Inc. All rights reserved.
Commands