MT48LC4M32LFF5-8 IT:G TR Micron Technology Inc, MT48LC4M32LFF5-8 IT:G TR Datasheet - Page 47
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MT48LC4M32LFF5-8 IT:G TR
Manufacturer Part Number
MT48LC4M32LFF5-8 IT:G TR
Description
DRAM Chip Mobile SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA T/R
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Datasheet
1.MT48LC8M16LFB4-75MG_TR.pdf
(80 pages)
Specifications of MT48LC4M32LFF5-8 IT:G TR
Density
128 Mb
Maximum Clock Rate
125 MHz
Package
90VFBGA
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
19|8|7 ns
Operating Temperature
-40 to 85 °C
Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
128M (4Mx32)
Speed
125MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
90-VFBGA
Organization
4Mx32
Address Bus
14b
Access Time (max)
19/8/7ns
Operating Supply Voltage (typ)
3.3V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
115mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 11:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
Current State
precharging
Activating,
precharge)
precharge)
(with auto
(with auto
precharge
precharge
active, or
disabled)
disabled)
Write
Write
(auto
(auto
Read
Read
Row
Any
Idle
Truth Table – CURRENT STATE BANK n, COMMAND tO BANK m
Notes 1–6 apply to entire table; notes appear below and on next page
CS#
Notes:
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS#
1. This table applies when CKE
2. This table describes alternate bank operation, except where noted; that is, the current state
3. Current state definitions:
4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
after
is for bank n and the commands shown are those allowed to be issued to bank m (assuming
that bank m is in such a state that the given command is allowable). Exceptions are covered
in the notes below.
when all banks are idle.
represented by the current state only.
precharge enabled:
precharge enabled:
CAS#
t
H
H
H
H
H
H
H
H
H
H
H
X
X
XSR has been met (if the previous state was self refresh).
L
L
L
L
L
L
L
L
L
L
Write w/auto
Read w/auto
Row active: A row in the bank has been activated, and
WE# Command (Action)
Write: A WRITE burst has been initiated, with auto precharge disabled, and
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
Read: A READ burst has been initiated, with auto precharge disabled, and
Idle: The bank has been precharged, and
COMMAND INHIBIT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command otherwise allowed to bank m
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
data bursts/accesses and no register accesses are in progress.
has not yet terminated or been terminated.
has not yet terminated or been terminated.
Starts with registration of a READ command with auto precharge
enabled and ends when
will be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled and ends when
will be in the idle state.
n - 1
47
was HIGH and CKE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
128Mb: x16, x32 Mobile SDRAM
RP has been met. After
RP has been met. After
n
is HIGH (see Table 9 on page 44) and
t
RP has been met.
©2001 Micron Technology, Inc. All rights reserved.
t
RCD has been met. No
t
t
RP is met, the bank
RP is met, the bank
7, 8, 14
7, 8, 15
7, 8, 16
7, 8, 17
Notes
READs
7, 10
7, 11
7, 12
7, 13
7
7
9
9
9
9