MT48LC4M32LFF5-8 IT:G TR Micron Technology Inc, MT48LC4M32LFF5-8 IT:G TR Datasheet - Page 68
![DRAM Chip Mobile SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA T/R](/photos/7/23/72313/mfg557-90-vfbga_sml.jpg)
MT48LC4M32LFF5-8 IT:G TR
Manufacturer Part Number
MT48LC4M32LFF5-8 IT:G TR
Description
DRAM Chip Mobile SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA T/R
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Datasheet
1.MT48LC8M16LFB4-75MG_TR.pdf
(80 pages)
Specifications of MT48LC4M32LFF5-8 IT:G TR
Density
128 Mb
Maximum Clock Rate
125 MHz
Package
90VFBGA
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
19|8|7 ns
Operating Temperature
-40 to 85 °C
Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
128M (4Mx32)
Speed
125MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
90-VFBGA
Organization
4Mx32
Address Bus
14b
Access Time (max)
19/8/7ns
Operating Supply Voltage (typ)
3.3V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
115mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Figure 47:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
DQMU, DQML
A0–A9, A11
COMMAND
BA0, BA1
A10
CLK
CKE
DQ
t CMS
t CKS
Alternating Bank Read Accesses
t AS
t AS
t AS
ACTIVE
BANK 0
T0
ROW
ROW
Notes:
t CKH
t CMH
t AH
t AH
t AH
t CK
t RCD - BANK 0
t RAS - BANK 0
t
t
RC - BANK 0
RRD
1. For this example, BL = 4 and CL = 2.
2. x16: A9 and A11 = “Don’t Care.”
T1
NOP
x32: A8, A9, and A11 = “Don’t Care.”
See Table 17 on page 53.
ENABLE AUTO PRECHARGE
t CMS
t CL
COLUMN m 2
BANK 0
T2
READ
t CMH
t CH
CAS Latency - BANK 0
T3
NOP
t LZ
t AC
68
BANK 3
ACTIVE
T4
ROW
ROW
D
OUT
t OH
t AC
m
t RCD - BANK 3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D
OUT
T5
NOP
m + 1
t OH
t AC
128Mb: x16, x32 Mobile SDRAM
ENABLE AUTO PRECHARGE
COLUMN b 2
D
BANK 3
T6
OUT
READ
m + 2
t OH
t AC
CAS Latency - BANK 3
UNDEFINED
©2001 Micron Technology, Inc. All rights reserved.
t RP - BANK 0
D
T7
OUT
NOP
Timing Diagrams
m + 3
t OH
t AC
BANK 0
T8
ROW
ACTIVE
ROW
D
OUT
t RCD - BANK 0
t OH
t AC
DON’T CARE
b