72261LA15TFI Integrated Device Technology (Idt), 72261LA15TFI Datasheet - Page 23

• Manufacturer Part Number: 72261LA15TFI
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 9 64-Pin STQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72261LA15TFI

• Package: 64STQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 144 Kb
• Organization: 16Kx9
• Data Bus Width: 9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: -40 to 85 °C

NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. t
5. PAE is asserted and updated on the rising edge of WCLK only.
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 16,384 for the IDT72261LA and 32,768 for the IDT72271LA.
2. For FWFT mode: D = maximum FIFO depth. D = 16,385 for the IDT72261LA and 32,769 for the IDT72271LA.
WCLK
WCLK
RCLK
IDT72261LA/72271LA SuperSync FIFO™
16,384 x 9 and 32,768 x 9
RCLK
WEN
WEN
REN
the rising edge of WCLK and the rising edge of RCLK is less than t
REN
SKEW2
PAE
HF
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus t
t
CLKH
t
ENS
n words in FIFO
n+1 words in FIFO
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
t
CLKL
t
[
ENH
D-1
t
(2)
SKEW2
2
1
,
D/2 words in FIFO
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
(3)
+ 1
(4)
]
words in FIFO
t
t
CLKH
PAE
(1)
,
2
(2)
SKEW2
t
ENS
, then the PAE deassertion may be delayed one extra RCLK cycle.
t
CLKL
23
t
t
ENH
t
ENS
HF
n+1 words in FIFO
n+2 words in FIFO
t
ENS
[
D-1
D/2 + 1 words in FIFO
t
2
ENH
+ 2
]
(2)
(3)
words in FIFO
,
t
HF
1
(1)
COMMERCIAL AND INDUSTRIAL
,
(2)
t
TEMPERATURE RANGES
PAE
PAE)
[
D-1
2
D/2 words in FIFO
. If the time between
2
+ 1
JANUARY 7, 2009
]
words in FIFO
n words in FIFO
n+1 words in FIFO
4671 drw 21
4671 drw 20
(1)
,
(2)
(2)
,
(3)