M4-128N/64-15JC LATTICE SEMICONDUCTOR, M4-128N/64-15JC Datasheet - Page 38

• Manufacturer Part Number: M4-128N/64-15JC
• Description: CPLD MACH 4 Family 5K Gates 128 Macro Cells 41.7MHz/55.6MHz EECMOS Technology 5V 84-Pin PLCC Tube
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of M4-128N/64-15JC

• Package: 84PLCC
• Family Name: MACH 4
• Device System Gates: 5000
• Number Of Macro Cells: 128
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 64
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 41.7|55.6 MHz
• Number Of Product Terms Per Macro: 20
• Re-programmability Support: Yes
• Operating Temperature: 0 to 70 °C

MACH 4 TIMING PARAMETERS OVER OPERATING RANGES
32
Combinatorial Delay:
t
t
Registered Delays:
t
t
t
t
t
t
t
t
t
t
Latched Delays:
t
t
t
t
t
t
t
t
t
t
Input Register Delays:
t
t
t
Input Latch Delays:
t
t
t
t
Input Register Delays with ZHT Option:
t
t
PDi
PD
SS
SST
SA
SAT
HS
HA
COSi
COS
COAi
COA
SSL
SAL
HSL
HAL
PDLi
PDL
GOSi
GOS
GOAi
GOA
SIRS
HIRS
ICOSi
SIL
HIL
IGOSi
PDILi
SIRZ
HIRZ
Internal combinatorial propagation delay
Combinatorial propagation delay
Synchronous clock setup time, D-type register
Synchronous clock setup time, T-type register
Asynchronous clock setup time, D-type register
Asynchronous clock setup time, T-type register
Synchronous clock hold time
Asynchronous clock hold time
Synchronous clock to internal output
Synchronous clock to output
Asynchronous clock to internal output
Asynchronous clock to output
Synchronous Latch setup time
Asynchronous Latch setup time
Synchronous Latch hold time
Asynchronous Latch hold time
Transparent latch to internal output
Propagation delay through transparent latch to output
Synchronous Gate to internal output
Synchronous Gate to output
Asynchronous Gate to internal output
Asynchronous Gate to output
Input register setup time
Input register hold time
Input register clock to internal feedback
Input latch setup time
Input latch hold time
Input latch gate to internal feedback
Transparent input latch to internal feedback
Input register setup time - ZHT
Input register hold time - ZHT
Min
5.5
6.5
3.5
4.5
0.0
3.5
6.0
4.0
0.0
4.0
2.0
3.0
2.0
3.0
6.0
0.0
MACH 4 Family
-7
Max
10.0
11.0
5.5
7.5
3.5
5.5
7.5
9.5
8.0
4.0
6.0
9.0
3.5
4.0
2.0
Min
6.0
7.0
4.0
5.0
0.0
4.0
7.0
4.0
0.0
4.0
2.0
3.0
2.0
3.0
6.0
0.0
-10
Max Min Max Min Max Min Max Min Max
10.0
10.0
12.0
10.0
12.0
11.0
13.0
8.0
4.5
6.5
5.5
7.5
4.5
4.0
2.0
7.0
8.0
5.0
6.0
0.0
5.0
8.0
5.0
0.0
5.0
2.0
3.0
2.0
3.0
6.0
0.0
-12
10.0
12.0
12.0
14.0
12.0
14.0
10.0
14.0
16.0
6.0
8.0
8.0
6.0
4.0
2.0
10.0
11.0
10.0
8.0
9.0
0.0
8.0
8.0
0.0
8.0
2.0
4.0
2.0
4.0
6.0
0.0
-14
12.0
14.0
10.0
16.0
18.0
15.0
17.0
11.0
17.0
19.0
8.0
9.0
6.0
5.0
2.0
1
10.0
11.0
10.0
8.0
9.0
0.0
8.0
8.0
0.0
8.0
2.0
4.0
2.0
4.0
6.0
0.0
-15
13.0
15.0
10.0
16.0
18.0
15.0
17.0
11.0
17.0
19.0
8.0
9.0
6.0
5.0
2.0
12.0
13.0
10.0
11.0
10.0
12.0
10.0
10.0
2.0
4.0
0.0
0.0
2.0
4.0
6.0
0.0
-18
16.0
18.0
10.0
12.0
18.0
20.0
18.0
20.0
10.0
12.0
20.0
22.0
6.0
6.0
2.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns