XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 119

no-image

XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC2VP7-5FF672C
Manufacturer:
XilinxInc
Quantity:
3 000
Part Number:
XC2VP7-5FF672C
Manufacturer:
XILINX
0
Part Number:
XC2VP7-5FF672C
Manufacturer:
ALTERA
0
Company:
Part Number:
XC2VP7-5FF672C
Manufacturer:
XILINX
Quantity:
1 582
Part Number:
XC2VP7-5FF672C
Manufacturer:
Xilinx Inc.
Quantity:
193
Part Number:
XC2VP7-5FF672C
Manufacturer:
XILINX
Quantity:
5
Part Number:
XC2VP7-5FF672C (TRAY)
Manufacturer:
XILINX
0
Miscellaneous Timing Parameters
Table 58: Miscellaneous Timing Parameters
Frequency Synthesis
Table 59: Frequency Synthesis
Parameter Cross-Reference
Table 60: Parameter Cross-Reference
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1. “DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
Time Required to Achieve LOCK
Fine Phase Shifting
Delay Lines
CLKFX_MULTIPLY
CLKFX_DIVIDE
DLL_CLKOUT_{MIN|MAX}_LF
DFS_CLKOUT_{MIN|MAX}_LF
DLL_CLKIN_{MIN|MAX}_LF
DFS_CLKIN_{MIN|MAX}_LF
DLL_CLKOUT_{MIN|MAX}_HF
DFS_CLKOUT_{MIN|MAX}_HF
DLL_CLKIN_{MIN|MAX}_HF
DFS_CLKIN_{MIN|MAX}_HF
Using DLL outputs
Using CLKFX outputs
Additional lock time with fine phase
shifting
Absolute shifting range
Tap delay resolution
Attribute
Description
R
(1)
Libraries Guide
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Min
2
1
LOCK_DLL_FINE_SHIFT
FINE_SHIFT_RANGE
LOCK_DLL_50_60
LOCK_DLL_40_50
LOCK_DLL_30_40
LOCK_DLL_24_30
DCM_TAP_MAX
LOCK_FX_MAX
LOCK_FX_MIN
DCM_TAP_MIN
LOCK_DLL_60
LOCK_DLL:
Symbol
Max
32
32
www.xilinx.com
CLKOUT_FREQ_{1X|2X|DV}_LF
CLKOUT_FREQ_FX_LF
CLKIN_FREQ_DLL_LF
CLKIN_FREQ_FX_LF
CLKOUT_FREQ_{1X|DV}_HF
CLKOUT_FREQ_FX_HF
CLKIN_FREQ_DLL_HF
CLKIN_FREQ_FX_HF
Constraints
50 - 60 MHz
40 - 50 MHz
30 - 40 MHz
24 - 30 MHz
> 60MHz
F
CLKIN
120.00
Data Sheet
-7
20.00
25.00
50.00
90.00
10.00
10.00
50.00
10.00
30.00
50.00
Speed Grade
120.00
-6
20.00
25.00
50.00
90.00
10.00
10.00
50.00
10.00
30.00
50.00
120.00
-5
20.00
25.00
50.00
90.00
10.00
10.00
50.00
10.00
30.00
50.00
Module 3 of 4
Units
ms
ms
us
us
us
us
us
us
ns
ps
ps
48

Related parts for XC2VP7-5FF672C