XC3S500E-4VQG100C Xilinx Inc, XC3S500E-4VQG100C Datasheet - Page 154
![FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 100-Pin VTQFP](/photos/6/70/67082/100-tqfp_sml.jpg)
XC3S500E-4VQG100C
Manufacturer Part Number
XC3S500E-4VQG100C
Description
FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 100-Pin VTQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S500E-4VQG100C
Package
100VTQFP
Family Name
Spartan®-3E
Device Logic Cells
10476
Device Logic Units
1164
Device System Gates
500000
Number Of Registers
9312
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
66
Ram Bits
368640
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
66
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
100-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1536 - KIT STARTER SPARTAN-3E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S500E-4VQG100C
Manufacturer:
XILINX32
Quantity:
344
Company:
Part Number:
XC3S500E-4VQG100C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S500E-4VQG100C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
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DC and Switching Characteristics
Slave Parallel Mode Timing
Table 117: Timing for the Slave Parallel Configuration Mode
154
(Open-Drain)
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
T
T
SMCKBY
SMDCC
SMCSCC
SMCCW
RDWR_B
PROG_B
Symbol
(Output)
D0 - D7
(Inputs)
It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0 - D7 bus.
INIT_B
(Input)
CSI_B
(Input)
(Input)
(Input)
CCLK
BUSY
(2)
The time from the rising transition on the CCLK pin to a signal transition at the
BUSY pin
The time from the setup of data at the D0-D7 pins to the active edge the CCLK
pin
Setup time on the CSI_B pin before the active edge of the CCLK pin
Setup time on the RDWR_B pin before active edge of the CCLK pin
High-Z
Figure 76: Waveforms for Slave Parallel Configuration
T
SMCCW
T
SMDCC
Description
Byte 0
T
SMCSCC
www.xilinx.com
T
SMCCD
Byte 1
T
SMCKBY
T
T
SCCH
MCCH
BUSY
1/F
Byte n
CCPAR
DS312-3 (v3.8) August 26, 2009
T
All Speed Grades
SMCKBY
11.0
10.0
23.0
Min
-
T
T
T
MCCL
SCCL
SMCCCS
Product Specification
Byte n+1
Max
12.0
-
-
-
DS312-3_02_103105
T
SMWCC
Units
High-Z
ns
ns
ns
ns
R
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