XC3S500E-4VQG100C Xilinx Inc, XC3S500E-4VQG100C Datasheet - Page 224
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XC3S500E-4VQG100C
Manufacturer Part Number
XC3S500E-4VQG100C
Description
FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 100-Pin VTQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S500E-4VQG100C
Package
100VTQFP
Family Name
Spartan®-3E
Device Logic Cells
10476
Device Logic Units
1164
Device System Gates
500000
Number Of Registers
9312
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
66
Ram Bits
368640
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
66
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
100-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1536 - KIT STARTER SPARTAN-3E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
XILINX32
Quantity:
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Company:
Part Number:
XC3S500E-4VQG100C
Manufacturer:
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Quantity:
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Quantity:
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Pinout Descriptions
FG484: 484-ball Fine-pitch Ball Grid Array
The 484-ball fine-pitch ball grid array, FG484, supports the
XC3S1600E FPGA.
Table 154
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web-
site at:
http://www.xilinx.com/support/documentation/data_sheets/s3e_pin.zip
Pinout Table
Table 154: FG484 Package Pinout
224
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
lists all the FG484 package pins. They are sorted
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO/VREF_0
IO_L01N_0
IO_L01P_0
IO_L03N_0/VREF_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L09N_0/VREF_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L11N_0
IO_L11P_0
XC3S1600E
Pin Name
FG484
G12
G15
Ball
B13
C14
E16
F16
H10
H15
C18
C19
A20
A21
A19
A18
C16
D16
A16
A17
B15
C15
F15
D14
E14
J11
G8
B6
C5
F9
VREF
VREF
VREF
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
www.xilinx.com
Table 154: FG484 Package Pinout (Continued)
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_L12N_0/VREF_0
IO_L12P_0
IO_L13N_0
IO_L13P_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L18N_0/GCLK5
IO_L18P_0/GCLK4
IO_L19N_0/GCLK7
IO_L19P_0/GCLK6
IO_L21N_0/GCLK11
IO_L21P_0/GCLK10
IO_L22N_0
IO_L22P_0
IO_L24N_0
IO_L24P_0
IO_L25N_0/VREF_0
IO_L25P_0
IO_L27N_0
IO_L27P_0
IO_L28N_0
IO_L28P_0
IO_L29N_0
IO_L29P_0
IO_L30N_0
IO_L30P_0
IO_L32N_0/VREF_0
IO_L32P_0
IO_L33N_0
IO_L33P_0
IO_L35N_0
IO_L35P_0
IO_L36N_0
IO_L36P_0
IO_L38N_0/VREF_0
IO_L38P_0
IO_L39N_0
IO_L39P_0
XC3S1600E
Pin Name
DS312-4 (v3.8) August 26, 2009
Product Specification
FG484
G14
G13
Ball
A14
A15
H14
H13
E12
C12
B12
B11
C11
D11
E11
A10
D10
C10
F13
J13
F12
A9
H8
H9
C9
B9
E9
D9
B8
A8
A6
A7
A4
A5
E7
D7
D6
D5
B4
B3
F7
F8
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
VREF
VREF
VREF
VREF
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
R