XC5VLX330-2FFG1760C Xilinx Inc, XC5VLX330-2FFG1760C Datasheet - Page 329
![FPGA Virtex®-5 Family 331776 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX330-2FFG1760C
Manufacturer Part Number
XC5VLX330-2FFG1760C
Description
FPGA Virtex®-5 Family 331776 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX330-2FFG1760C
Package
1760FCBGA
Family Name
Virtex®-5
Device Logic Units
331776
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
1200
Ram Bits
10616832
Number Of Logic Elements/cells
331776
Number Of Labs/clbs
25920
Total Ram Bits
10616832
Number Of I /o
1200
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1760-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML525-UNI-G - EVAL PLATFORM ROCKET IO VIRTEX-5HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Price
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Part Number:
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Manufacturer:
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Quantity:
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Part Number:
XC5VLX330-2FFG1760C
Manufacturer:
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Table 7-10: IODELAY Attribute Summary
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
IDELAY_TYPE
IDELAY_VALUE
ODELAY_VALUE
HIGH_PERFORMANCE_MODE Boolean: FALSE,
SIGNAL_PATTERN
REFCLK_FREQUENCY
DELAY_SRC
IODELAY Attributes
Attribute
Table 7-10
IDELAY_TYPE Attribute
The IDELAY_TYPE attribute sets the type of delay used. The attribute values are
DEFAULT, FIXED, and VARIABLE. When set to DEFAULT, the zero-hold time delay
element is selected. This delay element is used to guarantee non-positive hold times when
global clocks are used without DCMs to capture data (pin-to-pin parameters).
When set to FIXED, the tap-delay value is fixed at the number of taps determined by the
IDELAY_VALUE attribute setting. This value is preset and cannot be changed after
configuration.
When set to VARIABLE, the variable tap delay element is selected. The tap delay can be
incremented by setting CE = 1 and INC = 1, or decremented by CE = 1 and INC = 0. The
increment/decrement operation is synchronous to C, the input clock signal.
IDELAY_VALUE Attribute
The IDELAY_VALUE attribute specifies the initial number of tap delays. The possible
values are any integer from 0 to 63. The default value is zero. The value of the tap delay
reverts to IDELAY_VALUE when the tap delay is reset. In variable mode this attribute
determines the initial setting of the delay line.
String:
DEFAULT,
FIXED, or
VARIABLE
Integer: 0 to 63
Integer: 0 to 63
TRUE
String: DATA,
CLOCK
Real: 190.0 to
210.0
String: I, O, IO, or
DATAIN
summarizes the IODELAY attributes.
Value
www.xilinx.com
Default Value
DEFAULT
0
0
TRUE
DATA
200
DATAIN
Sets the type of tap delay line. Default delay is
used to guarantee zero hold times, fixed delay is
used to set a static delay value, and variable delay
is used to dynamically adjust the delay value.
Specifies the fixed number of delay taps in fixed
mode or the initial starting number of taps in
variable mode (input path).
Specifies the fixed number of delay taps (output
path).
When TRUE, this attribute reduces the output
jitter. The difference in power consumption is
quantified in the Xilinx Power Estimator tool.
The SIGNAL_PATTERN attribute causes the
timing analyzer to account for the appropriate
amount of delay-chain jitter in the data or clock
path.
IDELAYCTRL reference clock frequency (MHz).
I: IODELAY chain input is IDATAIN
O: IODELAY chain input is ODATAIN
IO: IODELAY chain input is IDATAIN and
ODATAIN (controlled by T)
DATAIN: IODELAY chain input is DATAIN
Input/Output Delay Element (IODELAY)
Description
329
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