XC5VLX330-2FFG1760C Xilinx Inc, XC5VLX330-2FFG1760C Datasheet - Page 369
![FPGA Virtex®-5 Family 331776 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX330-2FFG1760C
Manufacturer Part Number
XC5VLX330-2FFG1760C
Description
FPGA Virtex®-5 Family 331776 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX330-2FFG1760C
Package
1760FCBGA
Family Name
Virtex®-5
Device Logic Units
331776
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
1200
Ram Bits
10616832
Number Of Logic Elements/cells
331776
Number Of Labs/clbs
25920
Total Ram Bits
10616832
Number Of I /o
1200
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1760-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML525-UNI-G - EVAL PLATFORM ROCKET IO VIRTEX-5HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX330-2FFG1760C
Manufacturer:
INTEL
Quantity:
340
Company:
Part Number:
XC5VLX330-2FFG1760C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
X-Ref Target - Figure 8-13
Clock Event 4
The first two bits of the fourth word CD have been sampled into the input side registers of
the ISERDES. On this same edge of CLKDIV, the second word sampled is presented to
Q1–Q4 with one bit shifted to the right. The actual bits from the input stream that appear
at the Q1–Q4 outputs during this cycle are shown in B of
The realigned bits on Q1–Q4 are sampled into the FPGA logic on the CLKDIV domain. The
total latency from when the ISERDES captures the asserted Bitslip input to when the
realigned ISERDES outputs Q1–Q4 are sampled by CLKDIV is two CLKDIV cycles.
Clock Event 5
The third word sampled is presented to Q1–Q4 with three bits shifted to the left. The actual
bits from the input stream that appear at the Q1–Q4 outputs during this cycle are shown in
C of
Figure
C
A
B
8-13.
Q1–Q4 During Clock Event 3
(No Bitslip)
Q1–Q4 During Clock Event 4
(1st Bitslip, Rotate 1 Bit to Right)
Q1–Q4 During Clock Event 5
(2nd Bitslip, Rotate 3 Bits to Left)
Figure 8-13: Bits from Data Input Stream (D) of
www.xilinx.com
Input Serial-to-Parallel Logic Resources (ISERDES)
C D A B C D
C D A B C D
C D A B C D
Figure
A B C D A B
A B C D A B
A B C D A B
8-13.
Figure 8-12
ug190_c8_13_100307
C D
C D
C D
369
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