XC5VLX330-2FFG1760C Xilinx Inc, XC5VLX330-2FFG1760C Datasheet - Page 85

• Manufacturer Part Number: XC5VLX330-2FFG1760C
• Description: FPGA Virtex®-5 Family 331776 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX330-2FFG1760C

• Package: 1760FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 331776
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 1200
• Ram Bits: 10616832
• Number Of Logic Elements/cells: 331776
• Number Of Labs/clbs: 25920
• Total Ram Bits: 10616832
• Number Of I /o: 1200
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1760-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML525-UNI-G - EVAL PLATFORM ROCKET IO VIRTEX-5HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Fixed-Phase Shifting
In
in phase with the desired clock phase. The clock outputs are phase-shifted to appear
sometime later than the input clock, and the LOCKED signal is asserted.
X-Ref Target - Figure 2-18
•
Figure
Clock Event 1
Clock event 1 appears after the desired phase shifts are applied to the DCM. In this
example, the shifts are positive shifts. CLK0 and CLK2X are no longer aligned to
CLKIN. However, CLK0, and CLK2X are aligned to each other, while CLK90 and
CLK180 remain as 90° and 180° versions of CLK0. The LOCK signal is also asserted
once the clock outputs are ready.
2-18, the DCM outputs the correct frequency. However, the clock outputs are not
LOCKED
CLK180
CLK2X
CLK90
CLKIN
CLK0
Figure 2-18: Phase Shift Example: Fixed
www.xilinx.com
Lock Time
1
ug190_2_19_042406
DCM Timing Models
85