Si4711-A20-GM Silicon Laboratories Inc, Si4711-A20-GM Datasheet - Page 25

• Manufacturer Part Number: Si4711-A20-GM
• Description: RF Transmitter Broadcast FM Radio Trns w/RDS/RBDS
• Manufacturer: Silicon Laboratories Inc

Specifications of Si4711-A20-GM

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.9. RDS/RBDS Processor (Si4711 Only)
The Si4711 implements an RDS/RBDS* processor for
symbol encoding, block synchronization, and error
correction. Digital data can be transmitted with the
Si4711 RDS/RBDS encoding feature.
RDS transmission is supported with three different
modes. The first mode is the simplest mode and
requires no additional user support except for pre-
loading the desired RDS PI and PTY codes and up to
12 8-byte PS character strings. The Si4711 will transmit
the PI code and rotate through the transmission of the
PS character strings with no further control required
from outside the device. The second mode allows for
more complicated transmissions. The PI and PTY
codes are written to the device as in mode 1. The
remaining blocks (B, C, and D) are written to a 252 byte
buffer. This buffer can hold 42 sets of BCD blocks. The
Si4711 creates RDS groups by creating block A from
the PI code, concatenating blocks BCD from the buffer,
and rotating through the buffer. The BCD buffer is
circular; so, the pattern is repeated until the buffer is
changed. Finally, the third mode allows the outside
controller to burst data into the BCD buffer, which
emulates a FIFO. The data does not repeat, but, when
the buffer is nearly empty, the Si4711 signals the
outside device to initiate another data burst. This mode
permits the outside device to use any RDS functionality
(including open data applications) that it wants.
*Note: RDS/RBDS is referred to only as RDS throughout the
5.10. Tuning
The frequency synthesizer uses Silicon Laboratories’
proven technology including a completely integrated
VCO.
quadrature local oscillator signal used to upconvert the
low intermediate frequency to RF. The VCO frequency
is locked to the reference clock and adjusted with an
automatic frequency control (AFC) servo loop during
transmission.
The tuning frequency can be directly programmed with
commands. For example, to tune to 98.1 MHz, the user
writes
argument = 9810.
The Si4710/11 supports channel spacing of 50, 100, or
200 kHz.
5.11. Reference Clock
The Si4710/11 reference clock is programmable,
supporting RCLK frequencies from 31.130 kHz to
40 MHz. The RCLK frequency divided by an integer
number (the prescaler value) must fall in the range of
31,130 to 34,406 Hz. Therefore, the range of RCLK
remainder of this document.
The
the
TX_TUNE_FREQ
frequency
synthesizer
command
generates
with
the
Rev. 1.1
an
frequencies is not continuous below frequencies of
311.3 kHz. The default RCLK frequency is 32.768 kHz.
Please refer to “AN305: Si471x FM Transmitter
Programming Guide” for using other RCLK frequencies.
5.12. Control Interface
A serial port slave interface is provided; this allows an
external controller to send commands to the Si4710/11
and receive responses from the device. The serial port
can operate in three bus modes: 2-wire mode, SPI
mode, or 3-wire mode. The Si4710/11 selects the bus
mode by sampling the state of the GPO1 and
GPO2/INT pins on the rising edge of RST. The GPO1
pin includes an internal pull-up resistor that is
connected while RST is low, and the GPO2/INT pin
includes an internal pull-down resistor that is connected
while RST is low. Therefore, it is only necessary for the
user to actively drive pins that differ from these states.
After the rising edge of RST, the pins, GPO1 and
GPO2/INT, are used as general-purpose output (O) pins
as described in Section “5.13. GPO Outputs”. In any
bus mode, commands may only be sent after V
V
5.12.1. 2-Wire Control Interface Mode
When selecting 2-wire mode, the user must ensure that
SCLK is high during the rising edge of RST, and stays
high until after the first start condition. Also, a start
condition must not occur within 300 ns before the rising
edge of RST.
2-wire bus mode uses only the SCLK and SDIO pins for
signaling. A transaction begins with the START
condition, which occurs when SDIO falls while SCLK is
high. Next, the user drives an 8-bit control word serially
on SDIO, which is captured by the device on rising
edges of SCLK. The control word consists of a seven bit
device address followed by a read/write bit (read = 1,
write = 0). The Si4710/11 acknowledges the control
word by driving SDIO low on the next falling edge of
SCLK.
Although the Si4710/11 responds to only a single device
address, this address can be changed with the SEN pin
(note that the SEN pin is not used for signaling in 2-wire
Table 15. Bus Mode Select on Rising Edge of
DD
Bus Mode
supplies are applied.
2-Wire
3-Wire
SPI
0 (must drive)
Si4710/11-A20
GPO1
RST
1
1
1 (must drive)
GPO2/INT
0
0
IO
and
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