TDA8295HN/C1 NXP Semiconductors, TDA8295HN/C1 Datasheet - Page 50

• Manufacturer Part Number: TDA8295HN/C1
• Description: Modulator / Demodulator IF DEMODULATOR
• Manufacturer: NXP Semiconductors

Specifications of TDA8295HN/C1

• Package / Case: HVQFN-40
• Maximum Operating Temperature: + 70 C
• Maximum Power Dissipation: 490 mW
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.2 V, 3.3 V
• Supply Current: 0.136 A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: TDA8295HN/C1,557

NXP Semiconductors
TDA8295_1
Product data sheet
Table 63.
Legend: * = default value.
Table 64.
Table 65.
Legend: * = default value.
Bit
3 to 0
HVPLL_BUS bit
HVPLL_BUS[7]
HVPLL_BUS[6]
HVPLL_BUS[5]
HVPLL_BUS[4]
HVPLL_BUS[3]
HVPLL_BUS[2]
HVPLL_BUS[1]
HVPLL_BUS[0]
Bit
7
6
5
4 and 3 -
2
1
0
Symbol
GP2_CF[3:0] R/W
Symbol
CLK_INV_GP2 R/W
CLK_INV_GP1 R/W
CLK_INV_GP0 R/W
GP2_VAL
GP1_VAL
GP0_VAL
GPIOREG_1 register (address 45h) bit description
HVPLL bus mapping
GPIOREG_2 register (address 46h) bit description
Digital global standard low IF demodulator for analog TV and FM radio
Rev. 01 — 4 February 2008
Access Value
Access Value
R/W
R/W
R/W
R/W
0000
0001*
0011
0100
to
1011
XXXX
0*
0*
0*
-
1*
1*
1*
Description
It determines how the general purpose pin GPIO2 is
configured.
Description
With CLK_INV_GPx, the output clock polarity can be
changed. This is only useful when
GPx_CF[3:0] = 0011.
not used
GP2_VAL controls the value of the pin GPIO2 when
GP2_CF[3:0] = 0001. When GP2_CF[3:0] = 0000,
GPIO2 is an input pin which value can be read
through the I
GP1_VAL controls the value of the pin GPIO1 when
GP1_CF[3:0] = 0001. When GP1_CF[3:0] = 0000,
GPIO1 is an input pin which value can be read
through the I
GP0_VAL controls the value of the pin GPIO0 when
GP0_CF[3:0] = 0001. When GP0_CF[3:0] = 0000,
GPIO0 is an input pin which value can be read
through the I
The GPIO2 pin is in Input mode. The input value is
stored in GP2_VAL.
The GPIO2 pin is in Open-drain mode. The output
value is determined by GP2_VAL.
The GPIO2 pin is in Output mode. The PLL output
clock divided by two is delivered.
The GPIO2 pin is in Output mode. HVPLL signals are
delivered. The output is a one bit signal of
HVPLL_BUS[7:0] according to
Don’t care if I2CSW_EN = 1. Then the pad is
configured as I
Signal
V_SYNC
H_SYNC
NOISE_DET
MAC_DET
FIDT
V_LOCK
F_H_LOCK
N_H_LOCK
2
2
2
C-bus stored in GP2_VAL.
C-bus stored in GP1_VAL.
C-bus stored in GP0_VAL.
2
C-bus feed-through.
…continued
Table
TDA8295
© NXP B.V. 2008. All rights reserved.
64.
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