M54455EVB Freescale, M54455EVB Datasheet - Page 22

• Manufacturer Part Number: M54455EVB
• Manufacturer: Freescale

Specifications of M54455EVB

• Architecture: 32-bit (not ARM)
• Lead Free Status / RoHS Status: Supplier Unconfirmed

4.12
The M54455EVB provides a standard 40-pin ATA connector, as well as an external ATA data buffer that
interfaces with the MCF5445x processor's ATA interface.
A device connected to the ATA Interface must be powered by a separate supply. Several peripheral power
connectors are provided by the ATX power supply inside the case of the M54455EVB.
4.13
The M54455EVB FPGA is a Xilinx Spartan 3 FPGA that provides interrupt control for the four PCI slots
and the pushbuttons SW6 and SW7. It also provides a buffered FlexBus interface to the external
256K × 16bit MRAM and an interface to a seven-segment display and two LEDs.
4.13.1
The FPGA implements several FlexBus accessible memory-mapped registers.
memory map and the following sections provide details on each register.
0x0900_000C FPGA interrupt request routing register (FPGA_IRQROUTE)
22
0x0900_0000
0x0900_0004
0x0900_0008
0x0900_0010
0x0900_0014
0x0900_0018
Address
ATA
FPGA
FPGA Registers
FPGA interrupt request enable register (FPGA_IRQEN)
FPGA interrupt request status register (FPGA_IRQSTATUS)
FPGA PCI clock configuration register (FPGA_PCICLKCFG)
FPGA version register (FPGA_VERSION)
FPGA seven segment display register (FPGA_7SEGMENT)
FPGA LED control register (FPGA_LEDS)
The FEC1 RMII interface signals on the MCF5445x are multiplexed with
the upper eight bits of the ATA data bus. You must select between using the
FEC1 interface or the full ATA interface. The system’s CPLD provides
control for this selection. Refer to
Some of the ATA interface signals on the MCF5445x are multiplexed with
the FEC1 RMII interface signals. To have access to the full 16-bit ATA data
bus, the FEC1 interface must be disabled. The system’s CPLD provides
control for this selection. Refer to
Use only 32-bit reads and writes to these registers.
Register
M54455EVB User’s Manual, Rev. 4
Table 12. FPGA Memory Map
NOTE
NOTE
NOTE
Section 4.14,
Section 4.14,
“CPLD” for details.
“CPLD” for details.
Width
(bits)
32
32
32
32
32
32
32
Access Reset Value Section/Page
R/W
R/W
R/W
R/W
R/W
R
R
Table 12
0x0000_0004
0x0000_0039
0x1A00_0102
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Freescale Semiconductor
shows the
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