FW82371EB Intel, FW82371EB Datasheet - Page 11

• Manufacturer Part Number: FW82371EB
• Manufacturer: Intel

Specifications of FW82371EB

• Lead Free Status / RoHS Status: Not Compliant

Specification Changes
1.
2.
Specification Update
R
INTPN Register Not Implemented
The PIIX4 Datasheet section specified that the INTPN register indicates the PCI interrupt pin PIRQA# is
used for routing Serial Interrupts. However, Serial Interrupts are hardwired to IRQ9. This register is not
implemented.
This change applies to all steppings of the PIIX4 and PIIX4E and will be incorporated into the next
revision of the PIIX4 datasheet.
7.1.9 INTPN—INTERRUPT PIN (FUNCTION 3)
Address Offset:
Default Value:
Attribute:
This register indicates that PCI interrupt pin PIRQA# is used for the Power Management module.
Manual Throttle Duty Cycle
The throttle duty cycle bits (THTL_DTY) in the Processor Control Register (PCNTRL) are being
changed to match the ACPI specification.
This change applies to all steppings of the PIIX4E and will be incorporated into the next revision of the
PIIX4 datasheet.
7.2.7 PCNTRL —PROCESSOR CONTROL REGISTER (IO)
I/O Address:
Default Value:
Attribute
Bit
7:0
Bit
3:1
Not Implemented
Throttle Duty Programming Bits (THTL_DTY)—R/W. Selects the duty cycle of the
STPCLK# signal when the system is in the system throttling mode. The duty cycle indicates
the percentage of time the STPCLK# signal is asserted while in the throttle mode. The field is
decoded as follows:
Bits[2:0]
000
001
010
011
3Dh
00h
Read only
Base + (10h)
00h
Read/Write
Mode
Reserved
87.5%
75%
62.5%
Bits[2:0]
100
101
110
111
Description
Description
Mode
50%
37.5%
25%
12.5%
Intel
®
82371EB (PIIX4E)
11