FW82371EB Intel, FW82371EB Datasheet - Page 21

• Manufacturer Part Number: FW82371EB
• Manufacturer: Intel

Specifications of FW82371EB

• Lead Free Status / RoHS Status: Not Compliant

6.
Problem:
Implication: Accesses to devices in a powered down state could cause unpredictable results.
Workaround: Upon a powerdown event for devices 0-3 (IDE) the SMI handler must save the IDE register settings in
Status:
7.
Problem:
Implication: None, USB functionality is unaffected because the PIIX4 does meet the required output signal crossover
Workaround: None required.
Status:
8.
Problem:
Implication: An over-current condition could cause an unexpected system resume.
Workaround: None.
Status:
Specification Update
R
Device Trap
When the PIIX4 has the Device Trap logic enabled for Devices 0-13, it forwards the I/O access cycles
for the device to the EIO/ISA and IDE Bus.
CMOS, disable IORDY, and set PIO transfers for compatible timings. Upon a powerup event for
devices 0-3, the SMI handler must restore all original IDE register settings.
Upon a powerdown event for all other devices (using EIO), the SMI handler must disable the EIO
decode and enable the trap logic for that device. Upon a powerup event, the SMI handler must enable
the EIO decode and disable the trap logic.
This will not be fixed on PIIX4. This will be incorporated into the PIIX4 datasheet as a change to the
specification.
USB Rise/Fall Time Matching
The USB Specification defines a Rise / Fall Time Matching (T
Time by Fall Time (T
maximum. Simulation shows that the PIIX4 does not meet this specification.
voltage specifications (V
This will not be fixed on PIIX4. This will be incorporated into the PIIX4 datasheet as a change to the
specification.
System Resume on USB OC# Assertion
In POS, an oscillating CLK48 and an OC# assertion cause the USB_STS bit to be set triggering a system
resume. Typically systems turn off the CLK48 signal in POS which prevents the system resume.
However, after entering POS there is a short period of time as CLK48 turns off where it still oscillates.
An assertion of OC# before CLK48 completely stops can cause a system resume.
This will not be fixed on PIIX4. This will be incorporated into the PIIX4 datasheet as a change to the
specification.
R
/ T
CRS
F
). The specification for a full speed device is 90% minimum and 110%
).
RFM)
which is calculated by dividing Rise
Intel
®
82371EB (PIIX4E)
21