FW82371EB Intel, FW82371EB Datasheet - Page 25

• Manufacturer Part Number: FW82371EB
• Manufacturer: Intel

Specifications of FW82371EB

• Lead Free Status / RoHS Status: Not Compliant

16.
Problem:
Implication: The incorrect count causes the PIIX4 to confuse sector boundaries, resulting in invalid data being placed
Workaround: The workaround for this errata is to not perform Non-Data register reads while an IDE PIO transfer is
Status:
17.
Problem:
Implication: The errata condition can occur in Pentium® II processor/PIIX4E systems that use I/O Trap SMI with
Workaround: The I/O Trap SMI with I/O Restart feature should be disabled if STPCLK# throttling is used. For
Status:
Specification Update
R
IDE Prefetch
While executing a PIO IDE Read Sector(s) or Read Multiple command with PIO pre-fetching enabled, a
read of a non-Data Register (such as ALT STATUS Register) may cause the PIIX4 PIO pre-fetch
counter to increment, incorrectly since it should only increment on data transfers.
in memory. This erratum was observed during validation testing executing special test software. No
reports from internal testing or customer testing on production systems (i.e. without special test software)
have been attributed to this errata to date. Intel customers should perform there own risk analysis on this
errata and determine the most appropriate work around for their systems.
taking place. In cases where this errata has been seen, an interrupt (IRQn or SMI) has been used to enter
the code from which the ALT STATUS read occurs. Code which is not directly involved in the IDE
transfer should not perform the ALT STATUS read to check status of IDE transfers. An alternative for
PIIX4 based systems is to use IDE device idle timer to detect IDE activity. Another work around is to
disable IDE PIO prefetching.
This will not be fixed in the PIIX4. This will be incorporated into the PIIX4 datasheet as a Specification
Change. An additional paper titled “82371FB PIIX, 82371SB PIIX3, 82371AB PIIX4, 82371EB
PIIX4E IDE PREFETCH ERRATA DESCRIPTION is available from Intel which describes this errata
and risk analysis in greater detail. Intel is releasing this information to various operating system, BIOS
vendors, and other software developers to allow them to analyze their code base and to minimize the
potential for future software programs to trigger this errata.
SMI# Timing
When the PIIX4E asserts STPCLK# at the same time that it traps and I/O cycle, the SMI# assertion may
be delayed until 5 PCI clocks after STPCLK# is deasserted. If this occurs, the Pentium® II processor
will not recognize the SMI on the intended SMI code execution. If the I/O restart feature of the processor
is used, this could cause the processor to restart the wrong instruction, resulting in undefined processor
behavior. Software in which the instruction that follow the trapped I/O instruction is dependent on a
result returned by the I/O Trap SMI routine, may not execute correctly. PIIX4E I/O Trap SMI includes
device traps and APM register write traps (0B2h).
STPCLK# throttling enabled. The observed effect of the erratum is a system hang, although it may also
result in indeterminate code behavior which could cause data corruption.
applications where the I/O restart is not used, a dummy I/O instruction should follow the trapped I/O
instruction to ensure that the I/O trap SMI handler will be called before the result of that handler is
required. The system designer should review any I/O Trap SMI implementations for impact based on
their specific code execution sequence.
There are currently no plans to fix this erratum.
Intel
®
82371EB (PIIX4E)
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