EVAL-AD73322LEB Analog Devices Inc, EVAL-AD73322LEB Datasheet - Page 14

• Manufacturer Part Number: EVAL-AD73322LEB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD73322LEB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Analog Gain Tap
The analog gain tap is configured as a programmable differential
amplifier whose input is taken from the ADC’s input signal
path. The output of the analog gain tap is summed with the
output of the DAC. The gain is programmable using Control
Register F (CRF:0-4) to achieve a gain of –1 to +1 in 32 steps
with muting being achieved through a separate control setting
(Control Register F Bit 7). The gain increment per step is 0.0625.
The AGT is enabled by powering-up the AGT control bit in the
power control register (CRC:1). When this bit is set (=1) CRF
becomes an AGT control register with CRF:0-4 holding the
AGT coefficient, CRF:5 becomes an AGT enable and CRF:7
becomes an AGT mute control bit. Control bit CRF:5 connects/
disconnects the AGT output to the summer block at the output
of the DAC section while control bit CRF:7 overrides the gain
tap setting with a mute, (zero gain) setting. Table V shows the
gain versus digital setting for the AGT.
AGTC4 AGTC3 AGTC2 AGTC1
0
0
0
0
0
0
1
1
1
1
AD73322L
sigma-delta modulator’s positive input) being at a higher potential than VFBPx
(connected to the sigma-delta modulator’s negative input).
AGT and DGT weights are given for the case of VFBNx (connected to the
RESET
SDIFS
SDI
SE
CONTROL
REGISTER
0
0
0
0
0
1
0
1
1
1
1A
Table V. Analog Gain Tap Settings
8
EXTERNAL
DIVIDER
MCLK
MCLK
3
REGISTER
CONTROL
0
0
0
0
1
1
0
1
1
1
1B
8
REGISTER
REGISTER
DMCLK INTERNAL
CONTROL
CONTROL
16
SERIAL REGISTER 1
1G
1H
SERIAL PORT 1
0
0
1
1
0
1
0
0
1
1
REGISTER
CONTROL
(SPORT 1)
8
1C
REGISTER
CONTROL
1F
8
8
AGTC0 Gain (dB)
0
1
0
1
0
1
0
1
0
1
CONTROL
REGISTER
1D
8
DIVIDER
SCLK
2
+1.00
+0.9375
+0.875
+0.8125
+0.75
+0.0625
–0.0625
–0.875
–0.9375
–1.00
REGISTER
CONTROL
1E
SCLK
SDOFS1
SDO1
SDIFS2
Digital Gain Tap
The digital gain tap features a programmable gain block whose
input is taken from the bitstream output of the ADC’s sigma-
delta modulator. This single bit input (1 or 0) is used to add or
subtract a programmable value, which is the digital gain tap setting,
to the output of the DAC section’s interpolator. The program-
mable setting has 16-bit resolution and is programmed using the
settings in Control Registers G and H. (See Table VI).
Serial Port (SPORT)
The codecs communicate with a host processor via the bidirec-
tional synchronous serial port (SPORT), which is compatible
with most modern DSPs. The SPORT is used to transmit and
receive digital data and control information. The dual codec is
implemented using two separate codec blocks that are internally
cascaded with serial port access to the input of Codec1 and the
output of Codec2. This allows other single or dual codec devices to
be cascaded together (up to a limit of eight codec units).
RESET
AGT and DGT weights are given for the case of VFBNx (connected to the
sigma-delta modulator’s positive input) being at a higher potential than VFBPx
(connected to the sigma-delta modulator’s negative input).
CONTROL
REGISTER
SDI2
SE
2A
8
EXTERNAL
DIVIDER
MCLK
MCLK
3
REGISTER
CONTROL
Table VI. Digital Gain Tap Settings
DGT15–0 (Hex)
0x8000
0x9000
0xA000
0xC000
0xE000
0x0000
0x2000
0x4000
0x6000
0x7FFF
2B
8
REGISTER
REGISTER
DMCLK INTERNAL
CONTROL
CONTROL
16
SERIAL REGISTER 2
2G
2H
SERIAL PORT 2
REGISTER
CONTROL
(SPORT 2)
8
2C
CONTROL
REGISTER
2F
8
8
REGISTER
CONTROL
2D
Gain
–1.00
–0.875
–0.75
–0.5
–0.25
0.00
+0.25
+0.05
+0.75
+0.99999
8
DIVIDER
SCLK
2
REGISTER
CONTROL
2E
SDOFS
SDO