EVAL-AD73322LEB Analog Devices Inc, EVAL-AD73322LEB Datasheet - Page 29

• Manufacturer Part Number: EVAL-AD73322LEB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD73322LEB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Analog Output
The AD73322L’s differential analog output (VOUT) is produced
by an on-chip differential amplifier. The differential output can
be ac-coupled or dc-coupled directly to a load which can be a
headset or the input of an external amplifier (the specified mini-
mum resistive load on the output section is 150 Ω.) It is possible
to connect the outputs in either a differential or a single-ended
configuration but please note that the effective maximum output
voltage swing (peak to peak) is halved in the case of single-ended
connection. Figure 31 shows a simple circuit providing a differen-
tial output with ac coupling. The capacitors in this circuit (C
are optional; if used, their value can be chosen as follows:
where f
10 F
5V
R
R
A
R
B
C
LOAD
= desired cutoff frequency.
C2
C
C
C
ELECTRET
PROBE
REFCAP
OUT
OUT
R1
VOUTN1
REFOUT
VOUTP1
REFCAP
C
REFCAP
REFCAP
C1
VOUTP1
VOUTN1
REFOUT
R2
VFBN1
VINN1
VINP1
VFBP1
C
VFBN1
VINN1
V
VINP1
VFBP1
V
OUT
REF
REF
=
2π
+6/–15dB
+6/–15dB
GAIN
PGA
f R
PGA
C
1
1
REFERENCE
LOAD
GAIN
REFERENCE
1
CONTINUOUS
CONTINUOUS
LOW-PASS
LOW-PASS
FILTER
FILTER
TIME
TIME
AD73322L
AD73322L
V
REF
0/38dB
PGA
OUT
)
Figure 32 shows an example circuit for providing a single-ended
output with ac coupling. The capacitor of this circuit (C
not optional if dc current drain is to be avoided.
Differential to Single-Ended Output
In some applications it may be desirable to convert the full
differential output of the decoder channel to a single-ended
signal. The circuit of Figure 33 shows a scheme for doing this.
Digital Interfacing
The AD73322L is designed to easily interface to most common
DSPs. The SCLK, SDO, SDOFS, SDI and SDIFS must be
connected to the DSP’s Serial Clock, Receive Data, Receive
Data Frame Sync, Transmit Data and Transmit Data Frame
Sync pins respectively. The SE pin may be controlled from a
parallel output pin or flag pin such as FL0-2 on the ADSP-21xx
(or XF on the TMS320C5x) or, where SPORT power-down is not
required, it can be permanently strapped high using a suitable
pull-up resistor. The RESET pin may be connected to the sys-
tem hardware reset structure or it may also be controlled using a
dedicated control line. In the event of tying it to the global sys-
tem reset, it is advisable to operate the device in mixed mode,
which allows a software reset, otherwise there is no convenient
way of resetting the device. Figures 34 and 35 show typical
connections to an ADSP-218x and TMS320C5x respectively.
R
LOAD
R
LOAD
R
F
R
C
OUT
F
REFCAP
REFOUT
VOUTP1
VOUTN1
R
R
VFBN1
0.1 F
VINN1
VFBP1
VINP1
I
I
REFOUT
VOUTP1
VOUTN1
REFCAP
VFBN1
VFBP1
0.1 F
VINN1
VINP1
V
REF
V
REF
+6/–15dB
PGA
+6/–15dB
REFERENCE
PGA
GAIN
REFERENCE
1
CONTINUOUS
LOW-PASS
GAIN
FILTER
TIME
1
AD73322L
CONTINUOUS
LOW-PASS
FILTER
TIME
AD73322L
AD73322L
V
REF
OUT
0/38dB
PGA
) is