EVAL-AD73322LEB Analog Devices Inc, EVAL-AD73322LEB Datasheet - Page 34

• Manufacturer Part Number: EVAL-AD73322LEB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD73322LEB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

AD73322L
APPENDIX A
DAC Timing Control Example
The AD73322L’s DAC is loaded from the DAC register con-
tents just before the ADC register contents are loaded to the
serial register (SDOFS going high). This default DAC load
position can be advanced in time to occur earlier with respect to
the SDOFS going high. Figure 45 shows an example of the
ADC unload and DAC load sequence. At time t
raised to indicate that a new ADC word is ready. Following the
SDOFS pulse, 16 bits of ADC data are clocked out on SDO in
the subsequent 16 SCLK cycles finishing at time t
DSP’s SPORT will have received the 16-bit word. The DSP
FROM DAC REGISTER
DATA REGISTER
DAC LOAD
UPDATE
SDOFS
SDIFS
SCLK
SDO
SDI
SE
t
1
ADC WORD
1
the SDOFS is
2
where the
t
2
may process this information and generate a DAC word to be
sent to the AD73322L. Time t
sequence of sending the DAC word to the AD73322L. This
sequence ends at time t
from the 16 bits in the AD73322L’s serial register. However,
the DAC will not be updated from the DAC register until time
t
to reduce this delay and load the DAC at time t
advance register can be programmed with a suitable setting
corresponding to the required time advance (refer to Table X
for details of DAC Timing Control settings).
5
, which may not be acceptable in certain applications. In order
t
3
DAC WORD
t
4
t
4
6
where the DAC register will be updated
3
marks the beginning of the
t
5
6
, the DAC