XC5VLX110T-2FFG1738C Xilinx Inc, XC5VLX110T-2FFG1738C Datasheet - Page 170
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XC5VLX110T-2FFG1738C
Manufacturer Part Number
XC5VLX110T-2FFG1738C
Description
FPGA Virtex®-5 Family 110592 Cells 65nm (CMOS) Technology 1V 1738-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110T-2FFG1738C
Package
1738FCBGA
Family Name
Virtex®-5
Device Logic Units
110592
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
680
Ram Bits
5455872
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
5455872
Number Of I /o
680
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1738-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110T-2FFG1738C
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
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Chapter 4: Block RAM
Table 4-25: Block RAM ECC Mode Timing Parameters (Continued)
170
Notes:
1. T
2. T
3. T
4. T
Clock to ECC Delays
T
T
(encode-only mode)
T
T
Data Sheet.
RCKO_ECCR_DBITERR
RCKO_ECCR_SBITERR
RCKO_ECC_DBITERR
RCKO_ECC_SBITERR
T
RDCK_DI_ECC
RCKO_DO
RCKO_ECC_PARITY
RCKO_ECC_SBITERR
RCKO_ECC_PARITY
Parameter
Creating a Deliberate Error in a 72-bit Word
Creating Eight Parity Bits for a 64-bit Word
Inserting a Single or Double Bit Error into a 72-bit Word
includes parity output (T
/T
RCKD_DI_ECC
, T
and T
RCKO_ECC_SBITERR
(3)
(3)
(3)
(4)
(4)
To deliberately create an error in a 72-bit word, configure the ECC decode-only mode and
create a 72-bit word with one or two bit errors. Write the word into the block RAM.
Reading the 72-bit word automatically corrects the single-bit error and asserts the
SBITERR error flag or it detects the double-bit error and asserts the DBITERR error flag.
Using logic external to the block RAM (a large number of XOR circuits), eight parity bits
can be created for a 64-bit word. However, using ECC encoder-only mode, the eight parity
bits can be automatically created without additional logic by writing any 64-bit word into
a separate block RAM. The encoded 8-bit ECC parity data is immediately available, or the
complete 72-bit word can be read out.
By reading a 72-bit word and selectively modifying one or two bits, then writing all 72 bits
into the block RAM under test in ECC decode-only mode, a single or double bit error can
be inserted.
RCKO_ECC_DBITERR
Double-Bit-Error
Double-Bit-Error
Single-Bit-Error
Single-Bit-Error
include the parity input T
Parity Output
Clock to ECC
Clock to ECC
Clock to ECC
Clock to ECC
Clock to ECC
Function
Output
Output
Output
Output
RCKO_DOP
, and T
are combined into the T
RCKO_ECC_DBITERR
).
ECCPARITY
DBITERR
DBITERR
SBITERR
SBITERR
Control
Signal
www.xilinx.com
RDCK_DIP_ECC
are combined into the T
RCKO_ECCR
stable at the ECCPARITY outputs of the block RAM (in
encode-only mode).
Time after RDCLK that the single-bit-error signal is
stable at the SBITERR output of the block RAM
(without output register).
Time after RDCLK that the single-bit-error signal is
stable at the SBITERR output of the block RAM (with
output register).
Time after RDCLK that the double-bit-error signal is
stable at the DBITERR output of the block RAM
(without output register).
Time after RDCLK that the double-bit-error signal is
stable at the DBITERR output of the block RAM (with
output register).
Time after WRCLK that the ECC parity signals are
/T
RCKD_DIP_ECC
parameter in the Virtex-5 FPGA Data Sheet.
.
RCKO_ECC
Description
parameter in the Virtex-5 FPGA
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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