XC5VLX110T-2FFG1738C Xilinx Inc, XC5VLX110T-2FFG1738C Datasheet - Page 371
![FPGA Virtex®-5 Family 110592 Cells 65nm (CMOS) Technology 1V 1738-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX110T-2FFG1738C
Manufacturer Part Number
XC5VLX110T-2FFG1738C
Description
FPGA Virtex®-5 Family 110592 Cells 65nm (CMOS) Technology 1V 1738-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110T-2FFG1738C
Package
1738FCBGA
Family Name
Virtex®-5
Device Logic Units
110592
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
680
Ram Bits
5455872
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
5455872
Number Of I /o
680
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1738-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110T-2FFG1738C
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- XC5VLX30T-1FFG665C_PRODUCT_CHANGE PDF datasheet #4
- Current page: 371 of 385
- Download datasheet (14Mb)
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
OSERDES Primitive
3-State Parallel-to-Serial Conversion
Table 8-5: CLK/CLKDIV Relationship of the Data Parallel-to-Serial Converter
In addition to parallel-to-serial conversion of data, an OSERDES module also contains a
parallel-to-serial converter for 3-state control of the IOB. Unlike data conversion, the
3-state converter can only serialize up to four bits of parallel 3-state signals. The 3-state
converter cannot be cascaded.
The OSERDES primitive is shown in
X-Ref Target - Figure 8-15
Input Data Width Output in SDR
SHIFTIN1
SHIFTIN2
CLK
CLKDIV
D1
D2
D3
D4
D5
D6
OCE
SR
T1
T2
T3
T4
TCE
Mode
2
3
4
5
6
7
8
www.xilinx.com
Figure 8-15: OSERDES Primitive
Output Parallel-to-Serial Logic Resources (OSERDES)
Input Data Width Output in DDR
Figure
OSERDES
8-15.
Primitive
Mode
10
4
6
8
–
–
–
CLK
2X
3X
4X
5X
6X
7X
8X
ug190_8_15_100307
SHIFTOUT1
SHIFTOUT2
TQ
OQ
CLKDIV
X
X
X
X
X
X
X
371
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