XC5VLX110T-2FFG1738C Xilinx Inc, XC5VLX110T-2FFG1738C Datasheet - Page 67
![FPGA Virtex®-5 Family 110592 Cells 65nm (CMOS) Technology 1V 1738-Pin FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX110T-2FFG1738C
Manufacturer Part Number
XC5VLX110T-2FFG1738C
Description
FPGA Virtex®-5 Family 110592 Cells 65nm (CMOS) Technology 1V 1738-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110T-2FFG1738C
Package
1738FCBGA
Family Name
Virtex®-5
Device Logic Units
110592
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
680
Ram Bits
5455872
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
5455872
Number Of I /o
680
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1738-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX110T-2FFG1738C
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
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- Download datasheet (14Mb)
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Frequency Synthesis
Characteristics of the Deskew Circuit
Frequency Synthesis Operation
•
•
•
Source-Synchronous Setting
When DESKEW_ADJUST is set to source-synchronous mode, the DCM feedback delay
element is set to zero. As shown in
clock feedback delay element is set to minimize the sampling window. This results in a
more positive hold time and a longer clock-to-out compared to system-synchronous mode.
The source-synchronous switching characteristics section in the Virtex-5 FPGA Data Sheet
reflects the various timing parameters for the source-synchronous design when the DCM
is in source-synchronous mode.
•
•
•
•
•
•
•
•
The DCM provides several flexible methods for generating new clock frequencies. Each
method has a different operating frequency range and different AC characteristics. The
CLK2X and CLK2X180 outputs double the clock frequency. The CLKDV output provides a
divided output clock (lower frequency) with division options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5,
5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16.
The DCM also offers fully digital, dedicated frequency-synthesizer outputs CLKFX and its
opposite phase CLKFX180. The output frequency can be any function of the input clock
frequency described by M ÷ D, where M is the multiplier (numerator) and D is the divisor
(denominator).
The frequency synthesized outputs can drive the global-clock routing networks within the
device. The well-buffered global-clock distribution network minimizes clock skew due to
differences in distance or loading.
The DCM clock output CLKFX is any M ÷ D factor of the clock input to the DCM.
Specifications for M and D, as well as input and output frequency ranges for the frequency
synthesizer, are provided in the Virtex-5 FPGA Data Sheet.
Downstream DCMs when two or more DCMs are cascaded
DCMs with external feedback
DCMs with an external CLKIN that does not come from a dedicated clock input pin.
Eliminate clock distribution delay by effectively adding one clock period delay.
Clocks are deskewed to within CLKOUT_PHASE, specified in the Virtex-5 FPGA Data
Sheet.
Eliminate on-chip as well as off-chip clock delay.
No restrictions on the delay in the feedback clock path.
Requires a continuously running input clock.
Adapts to a wide range of frequencies. However, once locked to a frequency, large
input frequency variations are not tolerated.
Does not eliminate jitter. The deskew circuit output jitter is the accumulation of input
jitter and any added jitter value due to the deskew circuit.
The completion of configuration can be delayed until after DCM locks to guarantee
the system clock is established prior to initiating the device.
www.xilinx.com
Figure
2-4, in source-synchronous mode, the DCM
DCM Design Guidelines
67
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