BT1308W-400D,135 NXP Semiconductors, BT1308W-400D,135 Datasheet
BT1308W-400D,135
Specifications of BT1308W-400D,135
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BT1308W-400D,135 Summary of contents
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... Table 1. Pinning Pin Description 1 main terminal 1 (T1) 2 main terminal 2 (T2) 3 gate (G) 4 mounting base; main terminal 2 (T2) 400 V (BT1308W-400D) 600 V (BT1308W-600D ms) Simplified outline Product data sheet I Gate triggering in four quadrants I Direct interfacing to low-power gate drive circuits I Low-power AC fan speed controllers I I ...
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... Conditions BT1308W-400D BT1308W-600D full sine wave; T see Figure 4 and see Figure 2 and 16 mA T2 over any 20 ms period Rev. 01 — 27 February 2008 BT1308W series D Min - - 107 prior to surge / Triacs logic level Version SOT223 ...
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... Total power dissipation as a function of RMS on-state current; maximum values 12 I TSM ( Fig 2. Non-repetitive peak on-state current as a function of the number of sinusoidal current cycles; maximum values BT1308W_SER_D_1 Product data sheet 0.4 0 Rev. 01 — 27 February 2008 BT1308W series D Triacs logic level 003aac209 = 180 120 0 (A) T(RMS) 003aac207 TSM t 1/f ...
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... 107 Fig 4. RMS on-state current as a function of surge duration; maximum values BT1308W_SER_D_1 Product data sheet - 003aab489 I T(RMS) ( surge duration (s) Fig 5. Rev. 01 — 27 February 2008 BT1308W series max j(init 0.8 0.6 0.4 0 100 RMS on-state current as a function of solder point temperature; maximum values © ...
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... Transient thermal impedance from junction to solder point as a function of pulse width BT1308W_SER_D_1 Product data sheet Conditions full cycle; see Figure 6 full cycle for minimum footprint; see Figure 13 for pad area; see Figure Rev. 01 — 27 February 2008 BT1308W series D Triacs logic level Min Typ Max - - 15 - 156 - - © ...
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... A; see Figure 0 110 C D DRM 125 C D DRM(max 0. 110 C; DM DRM(max) j exponential waveform; gate open circuit DRM(max 0. /dt = 0.3 A/ms TM com mA DRM(max / Rev. 01 — 27 February 2008 BT1308W series D Triacs logic level Min Typ Max - 1.35 1.6 - 0.9 2 0.1 0 0.1 0 © NXP B.V. 2008. All rights reserved. ...
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... BT1308W_SER_D_1 Product data sheet 003aaa039 GT( 140 Fig 8. 003aab486 I L(25 C) (2) (3) 1.2 1 (V) T Fig 10. Normalized latching current as a function of Rev. 01 — 27 February 2008 BT1308W series D 3 (1) (2) 2 (3) (4) (1) (2) ( (1) T2 (4) T2+ G Normalized gate trigger current as a function of junction temperature ...
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... NXP Semiconductors Fig 11. Normalized holding current as a function of junction temperature BT1308W_SER_D_1 Product data sheet 2 H(25 C) 1.5 1.0 0 Rev. 01 — 27 February 2008 BT1308W series D Triacs logic level 003aaa032 90 140 © NXP B.V. 2008. All rights reserved ...
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... scale 0.32 6.7 3.7 7.3 4.6 2.3 0.22 6.3 3.3 6.7 REFERENCES JEDEC JEITA SC-73 Rev. 01 — 27 February 2008 BT1308W series detail 1.1 0.95 0.2 0.1 0.1 0.7 0.85 EUROPEAN PROJECTION Triacs logic level SOT223 ISSUE DATE 04-11-10 06-03-16 © NXP B.V. 2008. All rights reserved. ...
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... All dimensions are in mm All dimensions are in mm. Printed circuit board: FR4 epoxy glass (1.6 mm thick), copper laminate (35 m thick). Rev. 01 — 27 February 2008 BT1308W series D 3.8 min 6.3 2.3 4.6 001aab508 36 18 4.5 4 001aab509 Triacs logic level © ...
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... NXP Semiconductors 9. Revision history Table 6. Revision history Document ID Release date BT1308W_SER_D_1 20080227 BT1308W_SER_D_1 Product data sheet Data sheet status Change notice Product data sheet - Rev. 01 — 27 February 2008 BT1308W series D Triacs logic level Supersedes - © NXP B.V. 2008. All rights reserved ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 27 February 2008 BT1308W series D Triacs logic level © NXP B.V. 2008. All rights reserved ...
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... NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: BT1308W_SER_D_1 Triacs logic level All rights reserved. Date of release: 27 February 2008 ...