MPC9443FA IDT, Integrated Device Technology Inc, MPC9443FA Datasheet - Page 3

• Manufacturer Part Number: MPC9443FA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Dividerr

Specifications of MPC9443FA

• Number Of Clock Inputs: 3
• Output Frequency: 350MHz
• Output Logic Level: LVCMOS
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: LQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: LVCMOS/LVPECL
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Not Compliant

Table 2. Supported Single and Dual Supply Configurations
Table 3. . Function Table (Controls)
IDT™ / ICS™ LVCMOS CLOCK FANOUT BUFFER
3.3 V Supply
Mixed Mode Supply
2.5 V Supply
CCLK_SEL
PCLK_SEL
FSEL
FSEL
FSEL
FSEL
CLK_STOP
OE
1. V
2. V
3. V
4. V
5. V
Supply Voltage
MPC9443
2.5V, 3.3V LVCMOS CLOCK FANOUT BUFFER
Configuration
0
Control
, OE
Table 1. Pin Configuration
CCLK
PCLK0, PCLK0
PCLK1, PCLK1
FSEL
CCLK_SEL
PCLK_SEL
OE
CLK_STOP
GND
V
V
QA0 to QA4
QB0 to QB2
QC0 to QC2
QD0 to QD4
CC
CCA
CCB
CCC
CCD
A
B
C
D
CCA
CC
0
is the positive power supply of the device core and input circuitry. V
1
, OE
is the positive power supply of the bank A outputs. V
is the positive power supply of the bank B outputs. V
is the positive power supply of the bank C outputs. V
is the positive power supply of the bank D outputs. V
, V
A
, FSEL
CCB
1
, V
B
CCC
, FSEL
Default
Pin
00
0
0
0
0
0
0
0
, V
CCD
C
V
3.3 V
3.3 V
2.5 V
, FSEL
CC
(1)
PCLK or PCLK1 active (LVPECL clock mode)
PCLK0 active, PCLK1 inactive
f
f
f
f
Normal operation
QA0:4
QB0:2
QC0:2
QD0:4
D
= f
= f
= f
= f
REF
REF
REF
REF
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
3.3 V or 2.5 V
V
3.3 V
2.5 V
CCA
I/O
(2)
0
CCA
CCB
Asynchronous output enable control. See
CCC
CCD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Supply
Supply
Supply
LVCMOS
LVCMOS
LVCMOS
LVCMOS
3.3 V or 2.5 V
voltage defines bank A output levels.
voltage defines bank B output levels.
voltage defines bank C output levels.
voltage defines bank D output levels.
V
3.3 V
2.5 V
CCB
Type
(3)
3
CC
voltage defines the input threshold and levels.
LVCMOS clock inputs
LVPECL differential clock input
LVPECL differential clock input
Output bank divide select input
LVCMOS/LVPECL clock input select
PCLK0/PCLK1 clock input select
Output tristate control
Synchronous output enable/disable (clock stop) control
Negative voltage supply
Positive voltage supply output bank (V
Positive voltage supply core (V
Bank A outputs
Bank B outputs
Bank C outputs
Bank D outputs
3.3 V or 2.5 V
V
CCLK active (LVCMOS clock mode)
PCLK1 active, PCLK0 inactive
f
f
f
f
Outputs are synchronously disabled (stopped) in logic
low state
3.3 V
2.5 V
QA0:4
QB0:2
QC0:2
QD0:4
CCC
(4)
= f
= f
= f
= f
REF
REF
REF
REF
÷ 2
÷ 2
÷ 2
÷ 2
Table
3.3 V or 2.5 V
V
3.3 V
2.5 V
CCD
MPC9443 REV. 5 SEPTEMBER 19, 2008
Function
4.
(5)
1
CC
)
CC
)
GND
0 V
0 V
0 V