IDT5T93GL16NLI8 IDT, Integrated Device Technology Inc, IDT5T93GL16NLI8 Datasheet

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IDT5T93GL16NLI8

Manufacturer Part Number
IDT5T93GL16NLI8
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet

Specifications of IDT5T93GL16NLI8

Number Of Clock Inputs
2
Mode Of Operation
Differential
Output Frequency
650MHz
Output Logic Level
LVDS
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (typ)
2.5V
Operating Supply Voltage (max)
2.7V
Package Type
VFQFPN
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
52
Quiescent Current
350mA
Lead Free Status / RoHS Status
Not Compliant
General Description
The IDT5T93GL16 can act as a translator from a differential HSTL,
eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to
LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be
used to translate to LVDS outputs. The redundant input capability
allows for a glitchless change-over from a primary clock source to a
secondary clock source. Selectable inputs are controlled by SEL.
During the switchover, the output will disable low for up to three clock
cycles of the previously-selected input clock. The outputs will remain
low for up to three clock cycles of the newly-selected clock, after
which the outputs will start from the newly-selected input. A FSEL
pin has been implemented to control the switchover in cases where
a clock source is absent or is driven to DC levels below the minimum
specifications.
The IDT5T93GL16 outputs can be asynchronously
enabled/disabled. When disabled, the outputs will drive to the value
selected by the GL pin. Multiple power and grounds reduce noise.
Applications
IDT5T93GL16 REVISION B AUGUST 27, 2009
HiPerClockS™
ICS
Clock distribution
The IDT5T93GL16 2.5V differential clock buffer is a
user-selectable differential input to sixteen LVDS
outputs. The fanout from a differential input to sixteen
LVDS outputs reduces loading on the preceding driver
and provides an efficient clock distribution network.
2.5V LVDS, 1:16 Glitchless Clock
Buffer TERABUFFER™ II
1
Features
Guaranteed low skew: <25ps (maximum)
Very low duty cycle distortion: <100ps (maximum)
High speed propagation delay: <2ns (maximum)
Up to 650MHz operation
Glitchless input clock switching
Selectable inputs
Hot insertable and over-voltage tolerant inputs
3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL
(3.3V), CML or LVDS input interfaces
Selectable differential inputs to sixteen LVDS outputs
Power-down mode
At power-up, FSEL should be LOW
2.5V V
-40°C to 85°C ambient operating temperature
Available in VFQFPN package
Pin Assignment
V
V
Q2
Q2
G1
Q1
Q1
Q3
Q3
Q4
Q4
A1
A1
DD
DD
DD
11
1
2
3
4
5
6
7
8
9
10
12
13
52
14 15 16 17 18 19 20 21 22 23 24 25 26
51
50
IDT5T93GL16
52-Lead VFQFPN
49
48
K package
Top View
47 46 45 44 43 42 41 40
©2009 Integrated Device Technology, Inc.
IDT5T93GL16
39
38
37
36
35
34
33
32
31
30
29
28
27
DATA SHEET
G2
V
Q12
Q12
Q11
Q11
Q10
Q10
Q9
Q9
V
A2
A2
DD
DD

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IDT5T93GL16NLI8 Summary of contents

Page 1

LVDS, 1:16 Glitchless Clock Buffer TERABUFFER™ II General Description The IDT5T93GL16 2.5V differential clock buffer is a ICS user-selectable differential input to sixteen LVDS outputs. The fanout from a differential input to sixteen HiPerClockS™ LVDS outputs reduces loading on ...

Page 2

IDT5T93GL16 Data Sheet Block Diagram SEL FSEL G2 IDT5T93GL16 REVISION B AUGUST 27, 2009 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ OUTPUT CONTROL Q1 Q2 OUTPUT CONTROL Q2 Q3 ...

Page 3

IDT5T93GL16 Data Sheet Table 1. Pin Descriptions Name Type A[1:2] Input Adjustable A[1:2] Input Adjustable G1 Input LVTTL G2 Input LVTTL GL Input LVTTL Q[1:16] Output LVDS Q[1:16] Output LVDS SEL Input LVTTL PD Input LVTTL FSEL Input LVTTL V ...

Page 4

IDT5T93GL16 Data Sheet Table 2. Pin Characteristics Symbol Parameter C Input Capacitance IN NOTE: This parameter is measured at characterization but not tested. Function Tables Table 3A. Gate Control Output Table Control Outputs GL G Q[1:16 Toggling 0 ...

Page 5

IDT5T93GL16 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those ...

Page 6

IDT5T93GL16 Data Sheet Table 4B. LVTTL DC Characteristics Symbol Parameter I Input High Current IH I Input Low Current IL V Clamp Diode Voltage Input Voltage Input High Voltage Input Low ...

Page 7

IDT5T93GL16 Data Sheet Table 4D. LVDS DC Characteristics Symbol Parameter Differential Output Voltage for the V OT(+) True Binary State Differential Output Voltage for the V OT(–) False Binary State Change in V Between Complementary ∆ Output States ...

Page 8

IDT5T93GL16 Data Sheet Table 5C. LVEPECL (2.5V) and LVPECL (3.3V) Differential Input AC Characteristics, T Symbol Parameter (1) V Input Signal Swing DIF V Differential Input Signal Crossing Point X D Duty Cycle H V Input Timing Measurement Reference Level ...

Page 9

IDT5T93GL16 Data Sheet (1,5) Table 5F. AC Characteristics Symbol Parameter tsk(o) Same Device Output Pin-to-Pin Skew (3) tsk(p) Pulse Skew (4) tsk(pp) Part-to-Part Skew tp Propagation Delay, Low-to-High LH tp Propagation Delay, High-to-Low HL (6) fo Frequency Range Output Gate ...

Page 10

IDT5T93GL16 Data Sheet Differential AC Timing Waveforms Output Propagation and Skew Waveforms 1/ [1:2] [1:2] t PLH SK( NOTE 1: Pulse skew is calculated using the following expression ...

Page 11

IDT5T93GL16 Data Sheet Glitchless Output Operation with Switching Input Clock Selection SEL When SEL changes, the output clock goes LOW on the falling edge of the ...

Page 12

IDT5T93GL16 Data Sheet FSEL Operation for When Opposite Clock Dies 1. When the differential on the non-selected clock goes below the minimum DC differential, the outputs clock goes to an unknown state. When this happens, the FSEL pin should be ...

Page 13

IDT5T93GL16 Data Sheet Power Down Timing NOTE recommended that outputs be disabled before entering power-down mode also recommended that the ...

Page 14

IDT5T93GL16 Data Sheet Test Circuits and Conditions Test Circuit for Differential Input V IN Pulse Generator V IN Table 6A. Differential Input Test Conditions Symbol V = 2.5V ± 0. Crossing of A and A THI IDT5T93GL16 REVISION ...

Page 15

IDT5T93GL16 Data Sheet Test Circuit for DC Outputs and Power Down Tests V A Pulse Generator D.U.T. A Test Circuit for Propagation, Skew, and Gate Enable/Disable Timing A Pulse Generator D.U.T. A Table 6B. Differential Input Test Conditions Symbol V ...

Page 16

IDT5T93GL16 Data Sheet Recommended Landing Pattern Package Outline - K Suffix for 52 Lead VFQFPN 6.80 0.30 IDT5T93GL16 REVISION B AUGUST 27, 2009 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ II 8.40 3.60 0.50 6.80 16 ...

Page 17

IDT5T93GL16 Data Sheet Ordering Information Table 8. Ordering Information XX IDT XXXXX Device Type Package IDT5T93GL16 REVISION B AUGUST 27, 2009 X Process I NL NLG 5T93GL16 17 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER™ +85 ...

Page 18

IDT5T93GL16 Data Sheet Revision History Sheet Rev Table Page T3A 4 B T3B 4 IDT5T93GL16 REVISION B AUGUST 27, 2009 Description of Change Added Gate Control Output Table. Added Input Selection Table. Converted datasheet format. 18 2.5V LVDS 1:16 GLITCHLESS ...

Page 19

IDT5T93GL16 Data Sheet 6024 Silver Creek Valley Road Sales 800-345-7015 (inside USA) San Jose, California 95138 +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications ...

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