MC100ES6221TBR2 IDT, Integrated Device Technology Inc, MC100ES6221TBR2 Datasheet - Page 2

• Manufacturer Part Number: MC100ES6221TBR2
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of MC100ES6221TBR2

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 2000MHz
• Output Logic Level: ECL/PECL
• Operating Supply Voltage (min): -2.375/2.375V
• Operating Supply Voltage (typ): -2.5/-3.3/2.5/3.3V
• Operating Supply Voltage (max): -3.465/3.465V
• Package Type: TQFP EP
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Signal Type: ECL/HSTL/PECL
• Mounting: Surface Mount
• Pin Count: 52
• Quiescent Current: 160mA
• Lead Free Status / RoHS Status: Not Compliant

IDT™ Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES6221
Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer
Table 1. Pin Configuration
Table 2. Function Table
MC100ES6221
2
CLK0, CLK0
CLK1, CLK1
CLK_SEL
QA[0–19], QA[0–19]
V
V
V
CLK_SEL
1. In ECL mode (negative power supply mode), V
CLK_SEL
EE
CC
BB
power supply mode), V
referenced to the most positive supply (V
(1)
CLK0
CLK0
CLK1
CLK1
Pin
Figure 1. MC100ES6221 Logic Diagram
Pin
V
V
EE
V
V
EE
EE
CC
CLK0, CLK0 input pair is the reference clock. CLK0 can be
driven by ECL or PECL compatible signals.
V
CC
EE
Input
Input
Input
Output
Supply
Supply
Output
is connected to GND (0 V) and V
0
1
I/O
CC
).
0
ECL/PECL
HSTL
ECL/PECL
ECL/PECL
DC
•
•
•
EE
is either –3.3 V or –2.5 V and V
Type
V
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q16
Q16
Q17
Q17
Q18
Q18
Q19
Q19
•
•
•
BB
CC
is either +3.3 V or +2.5 V. In both modes, the input and output levels are
Differential reference clock signal input
Alternative differential reference clock signal input
Reference clock input select
Differential clock outputs
Negative power supply
Positive power supply. All V
power supply for correct DC and AC operation.
Reference voltage output for single ended ECL and PECL operation
2
V
Q5
Q5
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
CC
CLK1, CLK1 input pair is the reference clock. CLK1 can be
driven by HSTL compatible signals.
Figure 2. 52-Lead Package Pinout (Top View)
40
41
42
43
44
45
46
47
48
49
50
51
52
CC
39 38 37 36
1
is connected to GND (0 V). In PECL mode (positive
2
3
CC
4
pins must be connected to the positive
Function
35 34 33 32 31 30 29 28 27
MC100ES6221
5
6
Advanced Clock Drivers Devices
7
1
8
Freescale Semiconductor
9
10 11 12 13
26
25
24
23
22
21
20
19
18
17
16
15
14
MC100ES6221
NETCOM
Q12
Q12
Q13
Q13
Q14
Q14
Q15
Q15
Q16
Q16
Q17
Q17
V
CC