MC100ES6221TBR2 IDT, Integrated Device Technology Inc, MC100ES6221TBR2 Datasheet - Page 9

• Manufacturer Part Number: MC100ES6221TBR2
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of MC100ES6221TBR2

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 2000MHz
• Output Logic Level: ECL/PECL
• Operating Supply Voltage (min): -2.375/2.375V
• Operating Supply Voltage (typ): -2.5/-3.3/2.5/3.3V
• Operating Supply Voltage (max): -3.465/3.465V
• Package Type: TQFP EP
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Signal Type: ECL/HSTL/PECL
• Mounting: Surface Mount
• Pin Count: 52
• Quiescent Current: 160mA
• Lead Free Status / RoHS Status: Not Compliant

IDT™ Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES6221
Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer
Advanced Clock Drivers Devices
Freescale Semiconductor
Using the Thermally Enhanced Package of the
MC100ES6221
pad (EP) 52 lead LQFP package. The package is molded so
that the lead frame is exposed at the surface of the package
bottom side. The exposed metal pad will provide the low
thermal impedance that supports the power consumption of
the MC100ES6221 high-speed bipolar integrated circuit and
eases the power management task for the system design. A
thermal land pattern on the printed circuit board and thermal
vias are recommended in order to take advantage of the
enhanced thermal capabilities of the MC100ES6221. Direct
soldering of the exposed pad to the thermal land will provide
an efficient thermal path. In multilayer board designs, thermal
vias thermally connect the exposed pad to internal copper
planes. Number of vias, spacing, via diameters and land
pattern design depend on the application and the amount of
heat to be removed from the package. A nine thermal via
array, arranged in a 3 x 3 array and using a 1.2 mm pitch in
the center of the thermal land is a requirement for
MC100ES6221 applications on multi-layer boards. The
recommended thermal land design comprises a 3 x 3 thermal
via array as shown in
removal path.
copper via barrel plating. Solder wicking inside the via
resulting in voids during the solder process must be avoided.
If the copper plating does not plug the vias, stencil print solder
paste onto the printed circuit pad. This will supply enough
solder paste to fill those vias and not starve the solder joints.
The attachment process for exposed pad package is
equivalent to standard surface mount packages.
shows a recommend solder mask opening with respect to the
recommended 3 x 3 thermal via array. Because a large solder
mask opening may result in a poor release, the opening
should be subdivided as shown in
package standoff 0.1 mm, a stencil thickness of 5 to 8 mils
should be considered.
Thermal via array (3x3),
1.2 mm pitch,
0.3 mm diameter
The MC100ES6221 uses a thermally enhanced exposed
The via diameter is should be approx. 0.3 mm with 1 oz.
Figure 6. Recommended Thermal Land Pattern
Figure
4.8
6, providing an efficient heat
Figure
Exposed pad
land pattern
7. For the nominal
APPLICATIONS INFORMATION
Figure 7
all units mm
9
Thermal via array (3x3),
1.2 mm pitch,
0.3 mm diameter
calculation the thermal resistance parameters of the package
is provided:
Table 9. Thermal Resistance
analysis to assist in applying the general recommendations
to their particular application. The exposed pad of the
MC100ES6221 package does not have an electrical low
impedance path to the substrate of the integrated circuit and
its terminals. The thermal land should be connected to GND
through connection of internal board layers.
ConvectionL
1. Applicable for a 3 x 3 thermal via array.
2. Junction to ambient, four conductor layer test board (2S2P), per
3. Junction to ambient, single layer test board, per JESD51–3.
4. Junction to board, four conductor layer test board (2S2P) per
5. Junction to exposed pad.
6. Junction to top of package.
For thermal system analysis and junction temperature
It is recommended that users employ thermal modeling
Natural
JES51–7 and JESD 51–5.
JESD 51–8.
Figure 7. Recommended Solder Mask Openings
FPM
100
200
400
800
R
THJA
°C/W
20
18
17
16
15
(2)
0.2
4.8
R
°C/W
THJA
(1)
48
47
46
43
41
(3)
1.0
R
Exposed pad land
pattern
°C/W
29
4
THJC
(5)
(6)
MC100ES6221
all units mm
R
THJB
°C/W
16
MC100ES6221
NETCOM
(4)
9