MC100ES6222TBR2 IDT, Integrated Device Technology Inc, MC100ES6222TBR2 Datasheet - Page 6

• Manufacturer Part Number: MC100ES6222TBR2
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Dividerr

Specifications of MC100ES6222TBR2

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Logic Level: ECL/PECL
• Operating Supply Voltage (min): -2.375/2.375V
• Operating Supply Voltage (typ): -2.5/-3.3/2.5/3.3V
• Operating Supply Voltage (max): -3.465/3.465V
• Package Type: TQFP
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Signal Type: ECL/PECL
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Not Compliant

IDT™ / ICS™ ECL/PECL CLOCK DIVIDER AND FANOUT BUFFER
MC100ES6222
LOW VOLTAGE, 1:15 DIFFERENTIAL, ECL/PECL CLOCK DIVIDER AND FANOUT BUFFER
Table 7. AC Characteristics (ECL: V
Clock Input Pair CLK0, CLK0, CLK1, CLK1 (PECL or ECL differential signals)
ECL/PECL Clock Outputs (QA[0:1], QA[0:1], QB[0:2], QB[0:2], QC[0:3], QC[0:3], QD[0:5], QD[0:5]
1. AC characteristics apply for parallel output termination of 50 Ω to V
2. V
3. V
4. Output pulse skew is the absolute difference of the propagation delay times: | t
Symbol
V
t
t
V
JIT(CC)
t
t
sk(PP)
device-to-device skew.
V
propagation delay, device and part-to-part skew.
DC
f
O(P-P)
SK(P)
V
sk(O)
t
t
CLK
CMR
r
PD
PP
CMR
CMR
, t
PP
O
f
(AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tpd and
(AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the
(AC) range and the input swing lies within the V
Differential Input Voltage
Differential Input Crosspoint Voltage
Input Frequency
Propagation Delay
Differential Output Voltage (peak-to-peak)
Output-to-Output Skew
Output-to-Output Skew (part-to-part)
Output Cycle-to-Cycle Jitter
Output Pulse Skew
Output Duty Cycle
Output Rise/Fall Time
(PECL: V
(4)
Characteristics
(2)
(peak-to-peak)
EE
CC
= –3.3 V ± 5% or V
= 3.3 V ± 5% or V
(3)
CLK0 or CLK1 to Qx
f
f
f
REF
REF
REF
within QC[0:3]
within QD[0:5]
PP
within QA[0:1]
within QB[0:2]
f
f
O
O
(AC) specification. Violation of V
any output
< 1.0 GHz
< 2.0 GHz
< 0.1 GHz
< 1.0 GHz
< 2.0 GHz
RMS (1σ)
MR to Qx
PECL
EE
CC
ECL
= –2.5 V ± 5%, V
= 2.5 V ± 5%, V
TT
6
.
V
49.85
48.50
47.00
EE
TBD
TBD
Min
670
0.2
1.0
50
0
+1.0
pLH
– t
EE
pHL
CC
Typ
820
= GND, T
50
50
50
5
|.
= GND) or
CMR
(AC) or V
MC100ES6222 REV. 5 FEBRUARY 27, 2008
V
J
CC
–0.3 V
50.15
51.50
53.00
= 0°C to +110°C)
2000
Max
970
130
300
300
1.3
35
35
50
60
15
1
– 0.3
PP
ADVANCED CLOCK DRIVERS
(AC) impacts the device
MHz
Unit
mV
mV
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
%
%
V
V
V
Differential
Differential
Differential
Differential
DC
DC
DC
20% to 80%
(1)
REF
REF
REF
Condition
= 50%
= 50%
= 50%