MC100ES6222TBR2 IDT, Integrated Device Technology Inc, MC100ES6222TBR2 Datasheet - Page 9

• Manufacturer Part Number: MC100ES6222TBR2
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Dividerr

Specifications of MC100ES6222TBR2

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Logic Level: ECL/PECL
• Operating Supply Voltage (min): -2.375/2.375V
• Operating Supply Voltage (typ): -2.5/-3.3/2.5/3.3V
• Operating Supply Voltage (max): -3.465/3.465V
• Package Type: TQFP
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Signal Type: ECL/PECL
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Not Compliant

IDT™ / ICS™ ECL/PECL CLOCK DIVIDER AND FANOUT BUFFER
MC100ES6222
LOW VOLTAGE, 1:15 DIFFERENTIAL, ECL/PECL CLOCK DIVIDER AND FANOUT BUFFER
Using the Thermally Enhanced Package
of the MC100ES6222
pad (EP) 52 lead LQFP package. The package is molded so
the lead frame is exposed at the surface of the package
bottom side. The exposed metal pad will provide the low
thermal impedance supporting the power consumption of the
MC100ES6222 high-speed bipolar integrated circuit and
eases the power management task for the system design. A
thermal land pattern on the printed circuit board and thermal
vias are recommended in order to take advantage of the
enhanced thermal capabilities of the MC100ES6222. Direct
soldering of the exposed pad to the thermal land will provide
an efficient thermal path. In multilayer board designs, thermal
vias thermally connect the exposed pad to internal copper
planes. Number of vias, spacing, via diameters and land
pattern design depend on the application and the amount of
heat to be removed from the package. A nine thermal via
array, arranged in a 3 x 3 array and using a 1.2 mm pitch in
the center of the thermal land is a requirement for
MC100ES6222 applications on multi-layer boards. The
recommended thermal land design comprises a 3 x 3 thermal
via array as illustrated in
Land
1 ounce copper via barrel plating. Solder wicking inside the
via resulting in voids during the solder process must be
avoided. If the copper plating does not plug the vias, stencil
print solder paste onto the printed circuit pad. This will supply
enough solder paste to fill those vias and not starve the solder
joints. The attachment process for exposed pad package is
equivalent to standard surface mount packages.
Recommended Solder Mask Openings
recommend solder mask opening with respect to the
The MC100ES6222 uses a thermally enhanced exposed
The via diameter is should be approximately 0.3 mm with
Thermal via array (3x3),
1.2 mm pitch,
0.3 mm diameter
Figure 7. Recommended Thermal Land Pattern
Pattern, providing an efficient heat removal path.
Figure 7. Recommended Thermal
4.8
illustrates a
Exposed pad
land pattern
APPLICATIONS INFORMATION
All units mm
Figure 8.
9
recommended 3 x 3 thermal via array. Because a large solder
mask opening may result in a poor release, the opening
should be subdivided as illustrated in
Recommended Solder Mask
package standoff 0.1 mm, a stencil thickness of 5 to 8 mils
should be considered.
calculation the thermal resistance parameters of the package
is provided:
Table 9. Thermal Resistance
assist in applying the general recommendations to their
particular application. The exposed pad of the
MC100ES6222 package does not have an electrical low
impedance path to the substrate of the integrated circuit and
its terminals. The thermal land should be connected to GND
through connection of internal board layers.
1. Applicable for a 3 x 3 thermal via array
2. Junction to ambient, four conductor layer test board (2S2P), per
3. Junction to ambient, single layer test board, per JESD51-3
4. Junction to board, four conductor layer test board (2S2P) per
5. Junction to exposed pad
6. Junction to top of package
Convection
For thermal system analysis and junction temperature
It is recommended to employ thermal modeling analysis to
Thermal via array (3x3),
1.2 mm pitch,
0.3 mm diameter
JES51-7 and JESD 51-5
JESD 51-8
Natural
Figure 8. Recommended Solder Mask Openings
LFPM
100
200
400
800
R
THJA
°C/W
20
18
17
16
15
(2)
MC100ES6222 REV. 5 FEBRUARY 27, 2008
R
0.2
Openings. For the nominal
THJA
°C/W
4.8
(1)
48
47
46
43
41
(3)
Figure 8.
R
1.0
°C/W
29
THJC
4
(5)
Exposed pad land
pattern
(6)
All units mm
R
THJB
°C/W
16
(4)