IDT8523BGLF IDT, Integrated Device Technology Inc, IDT8523BGLF Datasheet - Page 3

IDT8523BGLF

Manufacturer Part Number
IDT8523BGLF
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet

Specifications of IDT8523BGLF

Number Of Clock Inputs
2
Mode Of Operation
Differential
Output Frequency
650MHz
Output Logic Level
HSTL
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Package Type
TSSOP
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
20
Lead Free Status / RoHS Status
Compliant
Function Tables
Table 3A. Control Input Function Table
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK, CLK and PCLK, PCLK inputs as described in Table 3B.
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
IDT™ / ICS™ HSTL FANOUT BUFFER
ICS8523
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
Baised; NOTE 1
Baised; NOTE 1
CLK, PCLK
CLK, PCLK
CLK or PCLK
CLK_EN
Q0:Q3
Q0:Q3
CLK_EN
0
1
0
1
0
0
1
1
Inputs
Baised; NOTE 1
Baised; NOTE 1
CLK or PCLK
0
1
0
1
CLK_SEL
Disabled
Inputs
0
1
0
1
Q[0:3]
HIGH
HIGH
HIGH
LOW
LOW
LOW
Selected Source
Outputs
PCLK, PCLK
PCLK, PCLK
CLK, CLK
CLK, CLK
3
Q[0:3]
HIGH
HIGH
HIGH
LOW
LOW
LOW
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Differential to Differential
Differential to Differential
Input to Output Mode
Disabled; LOW
Disabled; LOW
Enabled
Enabled
Enabled
Q0:Q3
ICS8523CGREV. D MARCH 13, 2007
Outputs
Disabled; HIGH
Disabled; HIGH
Enabled
Enabled
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Q0:Q3
Inverting
Inverting
Polarity

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