ICS8521BY IDT, Integrated Device Technology Inc, ICS8521BY Datasheet
ICS8521BY
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ICS8521BY Summary of contents
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G D ENERAL ESCRIPTION The ICS8521 is a low skew, 1-to-9 Differential-to-HSTL Fanout Buffer. The ICS8521 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, ...
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ABLE IN ESCRIPTIONS ...
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T 3A ABLE ONTROL NPUT UNCTION ...
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BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs Continuous Current Surge Current Package Thermal Impedance, θ JA Storage Temperature, T STG T 4A ABLE OWER UPPLY HARACTERISTICS S ...
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T 4D. LVPECL DC C ABLE HARACTERISTICS ...
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P ARAMETER 3.3V ± 5% 1.8V ± 0. DDO HSTL GND = 0V 3.3V C /1. ORE UTPUT OAD nQx Qx nQy Qy t sk( UTPUT KEW nCLK, nPCLK CLK, PCLK ...
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IRING THE IFFERENTIAL NPUT TO Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias ...
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IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL and other differential signals. Both V SWING V and V input requirements. Figures show PP CMR interface examples for the ...
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LVPECL LOCK NPUT NTERFACE The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both V and V SWING input requirements. Figures show interface and V CMR examples for the PCLK/nPCLK input driven ...
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This section provides information on power dissipation and junction temperature for the ICS8521. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8521 is the sum of the core power plus the power ...
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Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 5. F IGURE T o calculate worst case power dissipation into the ...
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ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row ...
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ACKAGE UTLINE UFFIX FOR EAD ABLE ...
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ABLE RDERING NFORMATION ...
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We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of ...