ICS8521BY IDT, Integrated Device Technology Inc, ICS8521BY Datasheet - Page 9

• Manufacturer Part Number: ICS8521BY
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS8521BY

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 500MHz
• Output Logic Level: HSTL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: LQFP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

8521BY
LVPECL C
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
and V
examples for the PCLK/nPCLK input driven by the most
common driver types. The input interfaces suggested here
F
F
F
IGURE
IGURE
IGURE
CMR
4A.
4C.
4E.
3.3V
3.3V
input requirements. Figures 4A to 4F show interface
2.5V
LVPECL
CML
SSTL
PCLK/nPCLK I
PCLK/nPCLK I
PCLK/nPCLK I
BY AN
LOCK
BY A
BY AN
3.3V LVPECL D
Zo = 50 Ohm
Zo = 50 Ohm
SSTL D
I
O
Zo = 50 Ohm
Zo = 50 Ohm
NPUT
Zo = 60 Ohm
Zo = 60 Ohm
PEN
C
SWING
I
NTERFACE
OLLECTOR
RIVER
NPUT
NPUT
NPUT
3.3V
R1
50
2.5V
R3
120
and V
3.3V
R3
125
R1
120
R1
84
D
D
D
R2
50
R4
120
RIVEN
RIVEN
RIVEN
RIVER
R2
120
R4
125
OH
CML D
R2
84
PCLK
nPCLK
must meet the V
3.3V
PCLK
nPCLK
PCLK
nPCLK
3.3V
HiPerClockS
PCLK/nPCLK
3.3V
RIVER
HiPerClockS
PCLK/nPCLK
Input
HiPerClockS
www.idt.com
PP
9
are examples only. If the driver is from another vendor, use
their termination recommendation. Please consult with the
vendor of the driver component to confirm the driver
termination requirements.
F
F
F
IGURE
IGURE
IGURE
3.3V
D
3.3V
IFFERENTIAL
3.3V
3.3V LVPECL
4B.
4D.
4F.
LVDS
CML Built-In Pullup
R5
100 - 200
PCLK/nPCLK I
PCLK/nPCLK I
PCLK/nPCLK I
BY A
BY A
BY A
Zo = 50 Ohm
Zo = 50 Ohm
R6
100 - 200
3.3V LVPECL D
3.3V LVDS D
B
Zo = 50 Ohm
Zo = 50 Ohm
UILT
-
R5
100
TO
-I
Zo = 50 Ohm
Zo = 50 Ohm
N
-HSTL F
P
NPUT
ULLUP
C1
C2
NPUT
NPUT
C1
C2
RIVER
L
3.3V
R3
84
D
D
D
R1
125
RIVER WITH
OW
R1
100
CML D
RIVEN
RIVEN
3.3V
R3
1K
RIVEN
R1
1K
R4
84
ANOUT
R2
125
S
R4
1K
PCLK
nPCLK
ICS8521
R2
1K
KEW
3.3V
RIVER
PCLK
nPCLK
REV. E JULY 25, 2010
HiPerClockS
PCLK/nPCLK
PCLK
nPCLK
AC C
3.3V
3.3V
, 1-
B
HiPerClockS
PCL K/n PC LK
HiPerClockS
PCLK/nPCLK
UFFER
OUPLE
TO
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